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ics for communications dsp embedded line and port interface controller delic-lc peb 20570 version 2.1 delic-pb peb 20571 version 2.1 preliminary data sheet 2003-08 ds 1.1
for questions on technology, delivery and prices please contact the infineon technologies offices in germany or the infineon technologies companies and representatives worldwide: see our webpage at http://www.infineon.com peb 20570 peb 20571 revision history: current version: 2003-08 previous version: 07.99 page (in previous version) page (in current version) subjects (major changes since last revision) trademarks changed edition 2003-08 published by infineon technologies ag, tr, balanstra?e 73, 81541 mnchen ? infineon technologies ag 5/8/03. all rights reserved. attention please! as far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. the information describes the type of component and shall not be considered as assured characteristics. terms of delivery and rights to change design reserved. due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies ag is an approved cecc manufacturer. packing please use the recycling operators known to you. we can also help you ? get in touch with your nearest sales office. by agreement we will take packing material back, if it is sorted. you must bear the costs of transport. for packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. components used in life-support devices or systems must be expressly authorized for such purpose! critical components 1 of the infineon technologies ag, may only be used in life-support devices or systems 2 with the express written approval of the infineon technologies ag. 1 a critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. if they fail, it is reasonable to assume that the health of the user may be en- dangered. abm ? , aop ? , arcofi ? , arcofi ? -ba, arcofi ? -sp, digitape ? , epic ? -1, epic ? -s, elic ? , falc ? 54, falc ? 56, falc ? -e1, falc ? -lh, idec ? , iom ? , iom ? -1, iom ? -2, ipat ? -2, isac ? -p, isac ? -s, isac ? -s te, isac ? -p te, itac ? , iwe ? , musac ? -a, octat ? -p, quat ? -s, sicat ? , sicofi ? , sicofi ? -2, sicofi ? -4, sicofi ? -4c, slicofi ? are registered trademarks of infineon technologies ag. ace ? , asm ? , asp ? , potswire ? , quadfalc ? , scout ? are trademarks of infineon technologies ag. note: ocem ? and oakdspcore ? (oak ? ) are registered trademarks of parthusceva, inc..
delic preliminary data sheet iii 2003-08 preface this document provides reference information on the delic-pb and -lc version 2.1. organization of this document this preliminary data sheet is divided into 11 chapters and appendices. it is organized as follows: chapter 1, introduction gives a general description of the product and its family, lists the key features, and presents some typical applications. chapter 2, pin description lists pin locations with associated signals, categorizes signals according to function, and describes signals. chapter 3, interface description describes the delic external interfaces. chapter 4, functional ic description describes the features of the main functional blocks. chapter 5, memory structure chapter 6, register descriptions containes the detailed register description. chapter 7, package outlines chapter 8, electrical characteristics containes the dc specification. chapter 9, timing diagrams contains the ac specification (as far as available). chapter 10, application hints chapter 11, mailbox protocol description describes the communication protocol to an external p.
delic preliminary data sheet iv 2003-08 your comments we welcome your comments on this document as we are continuously aiming at improving our documentation. please send your remarks and suggestions by e-mail to sc.docu_comments@infineon.com please provide in the subject of your e-mail: device name (delic-lc/ -pb), device number (peb 20570/ peb 20571), device version (version 2.1), or and in the body of your e-mail: document type (preliminary data sheet), issue date (2003-08) and document revision number (ds 1.1).
delic peb 20571 table of contents page preliminary data sheet v 2003-08 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 1.2 typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 2 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1 pin diagram delic-lc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.2 pin diagram delic-pb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.3 pin definitions and functions for delic-lc . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.4 pin definitions and functions for delic-pb . . . . . . . . . . . . . . . . . . . . . . 2-15 2.5 strap pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28 3 interface description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1 overview of interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.2 iom-2000 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.2.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.2.2 iom-2000 frame structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.2.2.1 data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.2.2.2 command and status interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.2.3 upn state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.2.3.1 info structure on the u pn interface . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.2.3.2 upn mode state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3.2.4 s/t state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 3.2.4.1 lt-s mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 3.2.4.2 lt-t mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 3.3 iom?-2 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23 3.3.1 signals / channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23 3.4 p interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24 3.4.1 intel/siemens or motorola mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24 3.4.2 de-multiplexed or multiplexed mode . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24 3.4.3 dma or non-dma mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25 3.4.4 delic external interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26 3.5 jtag test interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27 3.5.1 boundary scan test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27 3.5.2 tap controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27 4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.1 functional overview and block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2 iom-2000 transceiver unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.2.1 transiu overview of features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.2.2 transiu initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.2.3 initialization of vip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.2.4 s/t mode control and framing bits on iom-2000 . . . . . . . . . . . . . . . . 4-4 4.2.4.1 framing bit (f-bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.2.4.2 multiframing bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
delic peb 20571 table of contents page preliminary data sheet vi 2003-08 4.2.4.3 fa/n bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4.2.4.4 dc-balancing bit (l-bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4.2.5 upn mode control and framing bits on iom-2000 . . . . . . . . . . . . . . . 4-6 4.2.5.1 framing bit (lf-bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4.2.5.2 multiframing bit (m-bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4.2.5.3 dc-balancing bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4.2.6 iom-2000 command and status interface . . . . . . . . . . . . . . . . . . . . . . 4-7 4.2.7 iom-2000 data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 4.2.7.1 upn mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 4.2.7.2 upn scrambler/descrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 4.2.7.3 s/t mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 4.3 iom-2 unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14 4.3.1 iomu overview of features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14 4.3.2 iomu functional and operational description . . . . . . . . . . . . . . . . . . 4-15 4.3.2.1 frame-wise buffer swapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15 4.3.2.2 i-buffer logical structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15 4.3.2.3 dsp access to the d-buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16 4.3.2.4 iom-2 interface data rate modes . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16 4.3.2.5 iomu serial data processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18 4.3.2.6 iomu parallel data processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18 4.3.2.7 iom-2 push-pull and open-drain modes . . . . . . . . . . . . . . . . . . . . 4-19 4.3.2.8 support of drdy signal from quat-s . . . . . . . . . . . . . . . . . . . . . . 4-20 4.4 pcm unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21 4.4.1 pcmu functional and operational description . . . . . . . . . . . . . . . . . . 4-22 4.4.1.1 frame-wise buffer swapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22 4.4.1.2 dsp inaccessible buffer (i-buffer) . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22 4.4.1.3 dsp accessible buffer (d-buffer) . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23 4.4.1.4 pcmu interface data rate modes . . . . . . . . . . . . . . . . . . . . . . . . . 4-24 4.4.1.5 pcmu serial data processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-25 4.4.1.6 pcmu parallel data processing . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-25 4.4.1.7 pcmu tri-state control logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26 4.5 a-law/-law conversion unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-29 4.6 hdlc unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-30 4.6.1 hdlcu unit overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-30 4.6.2 dsp operation of the hdlcu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31 4.6.2.1 initialization of the hdlcu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31 4.6.2.2 transmitting a message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31 4.6.2.3 ending a transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32 4.6.2.4 aborting a transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32 4.6.2.5 dsp access to the hdlcu buffers . . . . . . . . . . . . . . . . . . . . . . . . . 4-32 4.7 ghdlc unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-34 4.7.1 ghdlc overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-34
delic peb 20571 table of contents page preliminary data sheet vii 2003-08 4.7.2 ghdlc channel external configurations . . . . . . . . . . . . . . . . . . . . . . 4-34 4.7.3 ghdlc general modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-34 4.7.4 ghdlc protocol features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-35 4.7.5 external configuration and handshaking in bus mode . . . . . . . . . . . . 4-35 4.7.5.1 external tri-state in point-to-multi-point mode . . . . . . . . . . . . . . . . 4-35 4.7.5.2 arbitration of ghdlcs on a collision bus . . . . . . . . . . . . . . . . . . . . 4-36 4.7.6 ghdlc memory allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-36 4.7.7 ghdlc interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-37 4.8 dsp control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-38 4.8.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-38 4.8.2 dsp address decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-38 4.8.3 interrupt handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-38 4.8.4 dsp run time statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-39 4.8.5 data bus and program bus arbitration . . . . . . . . . . . . . . . . . . . . . . . . 4-40 4.8.6 boot support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-40 4.8.7 reset execution and boot strap pin setting . . . . . . . . . . . . . . . . . . . . 4-41 4.9 general mailbox . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-42 4.9.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-42 4.9.2 p mailbox . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-42 4.9.3 oak mailbox . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-43 4.10 dma mailbox . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-45 4.10.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-45 4.10.2 intel/siemens mode and motorola mode (memory-to-memory) . . . . . 4-45 4.10.3 fly-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-45 4.10.4 pec mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-46 4.10.5 transmit mailbox . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-46 4.10.6 receive mailbox . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-47 4.10.7 access to the dma fifos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-48 4.11 dsp core oak+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-49 4.12 clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-50 4.12.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-50 4.12.2 dsp clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-52 4.12.3 pcm master/slave mode clocks selection . . . . . . . . . . . . . . . . . . . . . 4-52 4.12.4 delic clock system synchronization . . . . . . . . . . . . . . . . . . . . . . . . . 4-52 4.12.5 iom-2 clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-52 4.12.6 iom-2000 clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-53 4.12.7 refclk configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-53 4.12.8 ghdlc clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-53 5 delic memory structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1 dsp address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1.1 dsp register address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1.2 dsp program address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
delic peb 20571 table of contents page preliminary data sheet viii 2003-08 5.1.3 dsp data address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.2 p address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 6 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6.1 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6.2 detailed register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10 6.2.1 transiu register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10 6.2.1.1 transiu iom-2000 configuration register . . . . . . . . . . . . . . . . . . 6-10 6.2.1.2 transiu channel configuration registers . . . . . . . . . . . . . . . . . . 6-11 6.2.1.3 vip command registers (vipcmr0, vipcmr1, vipcmr2) . . . . . 6-12 6.2.1.4 vip status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14 6.2.1.5 transiu initialization channel command register . . . . . . . . . . . . 6-15 6.2.1.6 transiu initialization channel status register (ticstr) . . . . . . . 6-20 6.2.1.7 scrambler mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21 6.2.1.8 scrambler status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21 6.2.2 iomu register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22 6.2.2.1 iomu control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22 6.2.2.2 iomu status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23 6.2.2.3 iomu tri-state control register . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24 6.2.2.4 iomu drdy register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-25 6.2.2.5 iomu data prefix register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26 6.2.3 pcmu register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-27 6.2.3.1 pcmu command register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-27 6.2.3.2 pcmu status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-28 6.2.3.3 pcmu tri-state control registers . . . . . . . . . . . . . . . . . . . . . . . . . . 6-29 6.2.3.4 pcmu data prefix register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-30 6.2.4 a-/-law unit register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-31 6.2.4.1 a/-law unit control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-31 6.2.4.2 a/-law input register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-31 6.2.4.3 a/-law output register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-32 6.2.5 hdlcu registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-33 6.2.5.1 hdlcu control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-33 6.2.5.2 hdlcu status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-34 6.2.5.3 channel command vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-35 6.2.5.4 channel status vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-36 6.2.6 ghdlc register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-38 6.2.6.1 ghdlc test/ normal mode register . . . . . . . . . . . . . . . . . . . . . . . 6-38 6.2.6.2 ghdlc channel mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-38 6.2.6.3 ghdlc interrupt register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-39 6.2.6.4 ghdlc fsc interrupt control register . . . . . . . . . . . . . . . . . . . . . . 6-39 6.2.6.5 ghdlc receive channel status registers 0..3 . . . . . . . . . . . . . . . 6-40 6.2.6.6 ghdlc receive data and status . . . . . . . . . . . . . . . . . . . . . . . . . . 6-41 6.2.6.7 ghdlc mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-42
delic peb 20571 table of contents page preliminary data sheet ix 2003-08 6.2.6.8 ghdlc channel transmit command registers . . . . . . . . . . . . . . . 6-43 6.2.6.9 async control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-44 6.2.6.10 lclk0 control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-45 6.2.6.11 lclk1 control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-46 6.2.6.12 lclk2 control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-47 6.2.6.13 lclk3 control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-48 6.2.6.14 muxes control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-49 6.2.7 dcu register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-50 6.2.7.1 interrupt mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-50 6.2.7.2 status event register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-50 6.2.7.3 statistics counter register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-51 6.2.7.4 statistics register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-52 6.2.8 p configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-52 6.2.8.1 p interface configuration register . . . . . . . . . . . . . . . . . . . . . . . . . 6-52 6.2.8.2 device version register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-54 6.2.8.3 interrupt vector register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-54 6.2.9 p mailbox registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-55 6.2.9.1 p command register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-55 6.2.9.2 p mailbox busy register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-55 6.2.9.3 p mailbox generic data register . . . . . . . . . . . . . . . . . . . . . . . . . 6-56 6.2.9.4 p mailbox (general and dma mailbox) data registers . . . . . . . . . 6-57 6.2.9.5 dsp command register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-57 6.2.9.6 dsp mailbox busy register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-58 6.2.9.7 dsp mailbox generic data register . . . . . . . . . . . . . . . . . . . . . . . . 6-59 6.2.9.8 dsp mailbox (general and dma mailbox) data registers . . . . . . . 6-59 6.2.10 dma mailbox registers description . . . . . . . . . . . . . . . . . . . . . . . . . . 6-60 6.2.10.1 dma mailbox transmit counter register . . . . . . . . . . . . . . . . . . . . 6-60 6.2.10.2 dma mailbox receive counter register . . . . . . . . . . . . . . . . . . . . . 6-60 6.2.10.3 dma mailbox interrupt status register . . . . . . . . . . . . . . . . . . . . . . 6-61 6.2.11 clock generator register description . . . . . . . . . . . . . . . . . . . . . . . . . 6-62 6.2.11.1 pdc control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-62 6.2.11.2 pfs control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-62 6.2.11.3 clkout control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-63 6.2.11.4 dcxo reference clock select register . . . . . . . . . . . . . . . . . . . . . 6-64 6.2.11.5 refclk control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-65 6.2.11.6 dcl_2000 control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-66 6.2.11.7 dcl control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-66 6.2.11.8 fsc control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-67 6.2.11.9 l1_clk control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-68 6.2.11.10 pfs sync register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-69 6.2.11.11 realtime counter register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-69 6.2.11.12 strap status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-70
delic peb 20571 table of contents page preliminary data sheet x 2003-08 7 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 8 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8.2 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8.3 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 8.4 capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 8.5 recommended 16.384 mhz crystal parameters . . . . . . . . . . . . . . . . . . . 8-3 9 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9.2 p access timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9.2.1 p access timing in motorola mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9.2.2 p access timing in intel/infineon mode . . . . . . . . . . . . . . . . . . . . . . . . 9-3 9.3 interrupt acknowledge cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7 9.4 dma access timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9 9.4.1 dma access timing in motorola mode . . . . . . . . . . . . . . . . . . . . . . . . . 9-9 9.4.2 dma access timing in intel/infineon mode . . . . . . . . . . . . . . . . . . . . . 9-12 9.5 iom?-2 interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15 10 application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 10.1 delic connection to external microprocessors . . . . . . . . . . . . . . . . . . . 10-1 10.2 delic worksheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 11 mailbox protocol description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11.1 mailbox access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11.1.1 mailbox access transmit direction (p->delic) . . . . . . . . . . . . . . . . 11-1 11.1.2 mailbox access receive direction (delic->p) . . . . . . . . . . . . . . . . . 11-1 11.2 subscriber address (sad) interpretation . . . . . . . . . . . . . . . . . . . . . . . . 11-4 11.2.1 sad as iom-2 port and channel number . . . . . . . . . . . . . . . . . . . . . . 11-4 11.2.2 sad as iom-2000 vip and channel number . . . . . . . . . . . . . . . . . . . 11-5 11.3 overview of commands and indications . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 11.3.1 commands and indications for boot sequence . . . . . . . . . . . . . . . . . 11-5 11.3.2 general commands and indications . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 11.3.3 commands and indications for configuration . . . . . . . . . . . . . . . . . . . 11-7 11.3.4 commands and indications for iom-2 c/i channels . . . . . . . . . . . . . . 11-8 11.3.5 commands and indications for iom-2 monitor channel . . . . . . . . . . . 11-8 11.3.6 commands and indications for iom-2000 c/i channels . . . . . . . . . . . 11-9 11.3.7 commands and indications for hdlc channel . . . . . . . . . . . . . . . . . 11-10 11.3.8 commands and indications for ghdlc channel . . . . . . . . . . . . . . . 11-10 11.3.9 switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11 11.4 boot procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11 11.4.1 boot commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13 11.4.1.1 start boot command (0x55) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13
delic peb 20571 table of contents page preliminary data sheet xi 2003-08 11.4.1.2 finish boot command (0x1f) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13 11.4.1.3 write program memory command (0xan) . . . . . . . . . . . . . . . . . . 11-13 11.4.1.4 write data memory command (0xen) . . . . . . . . . . . . . . . . . . . . . . 11-14 11.4.2 boot indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-15 11.4.2.1 error indication (0b011100xx) . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-15 11.4.2.2 start loading program ram indication (0x1f) . . . . . . . . . . . . . . . 11-15 11.4.2.3 start loading data ram indication (0xef) . . . . . . . . . . . . . . . . . . 11-15 11.4.2.4 firmware version indication (0x00) . . . . . . . . . . . . . . . . . . . . . . . . 11-15 11.5 general commands and indications . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-16 11.5.1 general commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-16 11.5.1.1 write register command (0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . 11-16 11.5.1.2 read register command (0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . 11-17 11.5.2 general indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-18 11.5.2.1 read register indication (0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . 11-18 11.6 initialization/configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-19 11.6.1 configuration commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-20 11.6.1.1 iom-2000 reference channel select command (0x05) . . . . . . . . 11-20 11.6.1.2 iom-2000 delay measurement command (0x04) . . . . . . . . . . . . . 11-21 11.6.1.3 iom-2000 vip channel configuration command (0x03) . . . . . . . 11-22 11.6.1.4 ghdlc configuration command (0x14) . . . . . . . . . . . . . . . . . . . . 11-22 11.6.1.5 finish initialization command (0x06) . . . . . . . . . . . . . . . . . . . . . . . 11-24 11.6.2 configuration indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-24 11.6.2.1 iom-2000 far-end code violation indication (0x07) . . . . . . . . . . . 11-24 11.6.2.2 iom-2000 delay indication (0x04) . . . . . . . . . . . . . . . . . . . . . . . . . 11-25 11.6.2.3 finish vip channel configuration indication (0x02) . . . . . . . . . . . 11-26 11.7 iom-2 c/i handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-26 11.7.1 iom-2 c/i command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-27 11.7.1.1 write c/i value command (0x23) . . . . . . . . . . . . . . . . . . . . . . . . . 11-27 11.7.2 iom-2 c/i indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-27 11.7.2.1 change detected indication (0x41) . . . . . . . . . . . . . . . . . . . . . . . . 11-27 11.7.3 common mailbox parameter structure . . . . . . . . . . . . . . . . . . . . . . . 11-27 11.7.4 flow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-28 11.8 iom-2 monitor handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-29 11.8.1 iom-2 monitor commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-29 11.8.1.1 search on command (0x2b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-29 11.8.1.2 search reset command (0x2c) . . . . . . . . . . . . . . . . . . . . . . . . . . 11-30 11.8.1.3 monitor reset command (0x2d) . . . . . . . . . . . . . . . . . . . . . . . . . . 11-30 11.8.1.4 transmit continuous command (0x29) . . . . . . . . . . . . . . . . . . . . . 11-30 11.8.1.5 transmit command (0x28) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-30 11.8.1.6 transmit&receive/receive only command (0x2a) . . . . . . . . . . . 11-30 11.8.2 iom-2 monitor indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-31 11.8.2.1 transfer ready indication (0x53) . . . . . . . . . . . . . . . . . . . . . . . . . 11-31
delic peb 20571 table of contents page preliminary data sheet xii 2003-08 11.8.2.2 receive continuous indication (0x52) . . . . . . . . . . . . . . . . . . . . . . 11-31 11.8.2.3 receive indication (0x51) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-31 11.8.2.4 transmit abort indication (0x55) . . . . . . . . . . . . . . . . . . . . . . . . . . 11-32 11.8.2.5 monitor active indication (0x54) . . . . . . . . . . . . . . . . . . . . . . . . . . 11-32 11.8.3 common mailbox parameter structure . . . . . . . . . . . . . . . . . . . . . . . 11-32 11.8.4 flow diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-33 11.9 iom-2000 c/i handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-37 11.9.1 iom-2000 c/i command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-37 11.9.1.1 write c/i value command (0x0b) . . . . . . . . . . . . . . . . . . . . . . . . . 11-38 11.9.2 iom-2000 c/i indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-38 11.9.2.1 change detected indication (0x11) . . . . . . . . . . . . . . . . . . . . . . . . 11-38 11.9.3 common mailbox parameter structure . . . . . . . . . . . . . . . . . . . . . . . 11-38 11.10 hdlc handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-39 11.10.1 hdlc commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-39 11.10.1.1 reset command (0x1f) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-40 11.10.1.2 transmit command (0x1d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-41 11.10.1.3 transmit continuous command (0x1e) . . . . . . . . . . . . . . . . . . . . 11-41 11.10.1.4 activation/deactivation command (0x20) . . . . . . . . . . . . . . . . . . . 11-41 11.10.2 hdlc indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-42 11.10.2.1 error indication (0x34) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-42 11.10.2.2 transmit ready indication (0x33) . . . . . . . . . . . . . . . . . . . . . . . . . 11-43 11.10.2.3 receive indication (0x31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-44 11.10.2.4 receive continuous indication (0x32) . . . . . . . . . . . . . . . . . . . . . . 11-44 11.10.3 common mailbox parameter structure . . . . . . . . . . . . . . . . . . . . . . . 11-44 11.10.4 flow diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-45 11.11 ghdlc handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-46 11.11.1 ghdlc commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-46 11.11.1.1 reset command (0x15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-46 11.11.1.2 transmit command (0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-47 11.11.1.3 transmit continuous command (0x12) . . . . . . . . . . . . . . . . . . . . . 11-48 11.11.2 ghdlc indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-48 11.11.2.1 error indication (0x24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-48 11.11.2.2 fatal error indication (0x25) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-48 11.11.2.3 transmit ready indication (0x23) . . . . . . . . . . . . . . . . . . . . . . . . . 11-49 11.11.2.4 receive indication (0x21) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-49 11.11.2.5 receive continuous indication (0x22) . . . . . . . . . . . . . . . . . . . . . . 11-49 11.12 b-channel switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-50 11.12.1 switching commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-50 11.12.1.1 8-bit connect command (0x17) . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-50 11.12.1.2 8-bit disconnect command (0x18) . . . . . . . . . . . . . . . . . . . . . . . . 11-52 12 index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i-1
delic preliminary data sheet -xiii 2003-08 13 glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1
delic peb 20571 list of figures page preliminary data sheet xiv 2003-08 figure 1-1 block diagram of the delic-lc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 figure 1-2 block diagram of the delic-pb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 figure 1-1 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 figure 1-2 delic-lc in s/t and upn line cards (up to 8 s/t and 16 upn). . . . . 1-7 figure 1-3 delic-lc in uk0 line card for 16 subscribers. . . . . . . . . . . . . . . . . . 1-8 figure 1-4 delic-pb in analog line card for 16 subscribers . . . . . . . . . . . . . . . 1-8 figure 1-5 delic-pb in small pbx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 figure 2-1 pin configuration delic-lc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 figure 2-2 pin configuration delic-pb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 figure 3-1 overview of iom-2000 interface structure (example with one vip) . . 3-2 figure 3-2 iom-2000 data sequence (1 vip with 8 channels) . . . . . . . . . . . . . . 3-4 figure 3-3 iom-2000 data order (3 vips with 24 channels) . . . . . . . . . . . . . . . . 3-5 figure 3-4 iom-2000 cmd/stat handling (1 vip with 8 channels) . . . . . . . . . . 3-6 figure 3-5 iom-2000 command/status sequence (3 vips with 24 channels) . . 3-6 figure 3-6 upn state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 figure 3-7 state diagram of lt-s mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 figure 3-8 lt-t mode state diagram (conditional and unconditional states) . . 3-20 figure 3-9 iom?-2 interface in digital linecard mode . . . . . . . . . . . . . . . . . . . . 3-23 figure 3-10 delic in multiplexed and in de-multiplexed bus mode . . . . . . . . . . 3-25 figure 4-1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 figure 4-2 s/q channel assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 figure 4-3 iomu integration in delic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15 figure 4-4 iom-2 interface timing in single/double clock mode . . . . . . . . . . . . 4-18 figure 4-5 iom-2 interface open-drain mode . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19 figure 4-6 iom-2 interface push-pull mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19 figure 4-7 drdy signal behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20 figure 4-8 drdy sampling timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20 figure 4-9 pcmu integration in delic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22 figure 4-10 iom-2 interface timing in single/double clock mode . . . . . . . . . . . . 4-25 figure 4-11 hdlcu general block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-30 figure 4-12 data processing in the ghdlc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-34 figure 4-13 ghdlc interface lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-35 figure 4-14 ghdlc receive and transmit buffer structure . . . . . . . . . . . . . . . . 4-37 figure 4-15 statistics registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-39 figure 4-16 delic clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-51 figure 9-1 write cycle in motorola mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 figure 9-2 read cycle in motorola mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 figure 9-3 write cycle in intel/infineon de-multiplexed mode . . . . . . . . . . . . . . . 9-4 figure 9-4 read cycle in intel/infineon de-multiplexed mode . . . . . . . . . . . . . . . 9-5 figure 9-5 write cycle in intel/infineon multiplexed mode . . . . . . . . . . . . . . . . . . 9-6 figure 9-6 read cycle in intel/infineon multiplexed mode . . . . . . . . . . . . . . . . . . 9-7 figure 9-7 interrupt acknowledge cycle timing in motorola mode. . . . . . . . . . . . 9-8
delic peb 20571 list of figures page preliminary data sheet xv 2003-08 figure 9-8 interrupt acknowledge cycle timing in intel/infineon mode . . . . . . . . 9-8 figure 9-9 ireq deactivation timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9 figure 9-10 dma write transaction timing in motorola mode . . . . . . . . . . . . . . . 9-11 figure 9-11 dma read-transaction timing in motorola mode . . . . . . . . . . . . . . . 9-12 figure 9-12 dma write transaction timing in intel/infineon mode. . . . . . . . . . . . 9-14 figure 9-13 dma read transaction timing in intel/infineon mode . . . . . . . . . . . 9-14 figure 9-14 iom?-2 interface timing with single data rate dcl . . . . . . . . . . . . 9-15 figure 9-15 timing of the iom?-2 interface with double data rate dcl . . . . . . 9-16 figure 10-1 delic connection to intel 80386ex (demuxed configuration) . . . . 10-1 figure 10-2 delic connection to siemens c165 (demuxed configuration) . . . . 10-2 figure 10-3 delic-lc pcm unit mode 0 ( 4 ports with 2 mbit/s) . . . . . . . . . . . . . 10-3 figure 10-4 command/ indication handshake of general mailbox . . . . . . . . . . . . 10-4 figure 11-1 transmit mailbox structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 figure 11-2 receive mailbox structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 figure 11-3 flow diagram: mailbox write access . . . . . . . . . . . . . . . . . . . . . . . . 11-4 figure 11-4 boot sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12 figure 11-5 initialization flow diagram: configuration example. . . . . . . . . . . . . 11-20 figure 11-6 c/i flow diagram: receiving c/i value changes . . . . . . . . . . . . . . 11-29 figure 11-7 monitor flow diagram: transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-33 figure 11-8 monitor flow diagram: transmit continuous. . . . . . . . . . . . . . . . . . 11-34 figure 11-9 monitor flow diagram: search mode . . . . . . . . . . . . . . . . . . . . . . . 11-35 figure 11-10 monitor flow diagram: receive only with receive continuous . . . 11-36 figure 11-11 monitor flow diagram: transmit & receive. . . . . . . . . . . . . . . . . . . 11-37 figure 11-12 hdlc frame structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-39 figure 11-13 hdlc flow diagram: transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-45 figure 11-14 hdlc flow diagram: transmit continuous . . . . . . . . . . . . . . . . . . . 11-45
delic peb 20571 list of tables page preliminary data sheet xvi 2003-08 table 2-1 iom?-2 interface pins (delic-lc) . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 table 2-2 iom-2000 interface / lnc port 1 (delic-lc) . . . . . . . . . . . . . . . . . . 2-4 table 2-3 lnc port 0 (delic-lc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 table 2-4 microprocessor bus interface pins (delic-lc). . . . . . . . . . . . . . . . . 2-6 table 2-5 pcm interface ports 0 ... 3 / lnc ports 2 ... 3 (delic-lc) . . . . . . . . 2-8 table 2-6 clock generator pins (delic-lc) (additionally to iom/pcm clocks) 2-11 table 2-7 power supply pins (delic-lc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 table 2-8 jtag and emulation interface pins (delic-lc) . . . . . . . . . . . . . . . 2-13 table 2-9 test interface pins (delic-lc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 table 2-10 iom?-2 interface pins (delic-pb) . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 table 2-11 iom-2000 interface / lnc port 1 (delic-pb) . . . . . . . . . . . . . . . . . 2-16 table 2-12 lnc port 0 (delic-pb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 table 2-13 microprocessor bus interface pins (d elic-pb) . . . . . . . . . . . . . . . 2-18 table 2-14 pcm interface ports 0 ... 3 / lnc ports 2 ... 3 (delic-pb) . . . . . . . 2-20 table 2-15 clock generator pins (delic-pb) (additionally to iom/pcm clocks) 2-24 table 2-16 power supply pins (delic-pb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25 table 2-17 jtag and emulation interface pins (delic-pb) . . . . . . . . . . . . . . . 2-26 table 2-18 test interface pins (delic-pb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27 table 2-19 strap pins (evaluated during reset) . . . . . . . . . . . . . . . . . . . . . . . . 2-28 table 3-1 control bits in s/t mode on dr line . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 table 3-2 control bits in s/t mode on dx line . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 table 3-3 info structure on upn interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 table 3-4 upn state machine codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 table 3-5 lt-s state machine codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 table 3-6 lt-t mode state machine codes (conditional states) . . . . . . . . . . 3-18 table 3-7 tap controller instruction codes . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27 table 4-1 differences between delic-lc - delic-pb . . . . . . . . . . . . . . . . . . . 4-1 table 4-2 s/t mode multiframe bit positions . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 table 4-3 i-buffer logical memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16 table 4-4 d-buffer address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16 table 4-5 dcl frequency in different iom-2 modes. . . . . . . . . . . . . . . . . . . . 4-17 table 4-6 i-buffer logical memory mapping of input buffers. . . . . . . . . . . . . . 4-23 table 4-7 i-buffer logical memory mapping of output buffers . . . . . . . . . . . . 4-23 table 4-8 dsp access to d-buffer input blocks . . . . . . . . . . . . . . . . . . . . . . . 4-23 table 4-9 dsp access to d-buffer output blocks . . . . . . . . . . . . . . . . . . . . . . 4-24 table 4-10 pcm tsc in 4 x 32 ts mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26 table 4-11 pcm tsc in 2 x 64 ts mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-27 table 4-12 pcm tsc in 1 x 128 ts and 1 x 256 ts (1st half) mode . . . . . . . . 4-27 table 4-13 pcm tsc in 1 x 256 ts (2nd half) mode . . . . . . . . . . . . . . . . . . . . 4-27 table 4-14 interrupt map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-38 table 4-15 overview of clock signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-50 table 5-1 dsp registers address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
delic peb 20571 list of tables page preliminary data sheet xvii 2003-08 table 5-2 dsp program address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 table 5-3 occupied dsp data address space . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 table 5-4 oak memory mapped registers address space . . . . . . . . . . . . . . . . 5-3 table 5-5 p address space table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 table 6-1 transiu register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 table 6-2 scrambler register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 table 6-3 iomu register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 table 6-4 pcmu register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 table 6-5 a-/-law unit register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 table 6-6 hdlcu register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 table 6-7 ghdlc register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 table 6-8 dcu register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 table 6-9 p configuration register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 table 6-10 general mailbox register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 table 6-11 dma mailbox register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 table 6-12 clock generator register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9 table 6-13 available isdn modes for each vip channel . . . . . . . . . . . . . . . . . 6-11 table 6-14 tristate control assignment for iom-2 time slots. . . . . . . . . . . . . . 6-24 table 9-1 timing for write cycle in motorola mode . . . . . . . . . . . . . . . . . . . . . 9-2 table 9-2 timing for read cycle in motorola mode . . . . . . . . . . . . . . . . . . . . . 9-3 table 9-3 timing for write cycle in intel/infineon demultiplexed mode . . . . . . 9-4 table 9-4 timing for read cycle in intel/infineon de-multiplexed mode . . . . . 9-5 table 9-5 timing for write cycle in intel/infineon multiplexed mode . . . . . . . . 9-6 table 9-6 timing for read cycle in intel/infineon multiplexed mode . . . . . . . . 9-7 table 9-7 interrupt acknowledge cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . 9-8 table 9-8 r/w behavior during dma transactions in normal and fly-by mode 9-9 table 9-9 dma transaction timing in mototrola mode . . . . . . . . . . . . . . . . . . . 9-10 table 9-10 r/w behavior during dma transactions in normal and fly-by mode 9- 13 table 9-11 dma transaction timing in intel/infineon mode . . . . . . . . . . . . . . . 9-13 table 9-12 timing characteristics of the iom ? -2 . . . . . . . . . . . . . . . . . . . . . 9-15 table 9-13 timing characteristics of the iom ? -2 . . . . . . . . . . . . . . . . . . . . . 9-16 table 11-1 boot commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 table 11-2 boot indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 table 11-3 general commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 table 11-4 general indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 table 11-5 configuration commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7 table 11-6 configuration indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7 table 11-7 iom-2 c/i command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8 table 11-8 iom-2 c/i indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8 table 11-9 iom-2 monitor commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8 table 11-10 iom-2 monitor indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9
delic preliminary data sheet -xviii 2003-08 table 11-11 iom-2000 c/i command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9 table 11-12 iom-2000 c/i indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9 table 11-13 hdlc commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10 table 11-14 hdlc indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10 table 11-15 ghdlc commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10 table 11-16 ghdlc indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11 table 11-17 switching commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11 table 11-18 time slot address ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-50
delic introduction preliminary data sheet 1-1 2003-08 1 introduction the delic and vip chipset realizes multiple isdn s/t and up interfaces together with controller functionality typically needed in pbx or central office systems. this functionality comprises voice channel handling, signaling control, layer-1 control, and even signal processing tasks. moreover it provides a programmable master/slave clock generator with 2 plls, an universal p interface and a dma interface. the controller part, delic, is planned in three different versions: delic-lc ( peb 20570 ) is a line card controller providing voice channel switching, multiple hdlc and layer-1 control for up to three vips (24 isdn channels). other transceiver ics (32 analog or 16 digital channels) may additionally be connected via iom-2/gci interface. delic-pb (peb 20571 ) additionally provides a programmable telecom dsp including program and data ram. this dsp can be used for layer-1 control, protocol support and signal processing. the flexibility gained by the programmability allows infineon to offer different application specific solutions with the same silicon just by software configuration. a configuration tool assists the user in finding a valid system configuration. even more customer specific dsp-routines can be integrated with the assistance of infineon. delic-hd ( peb 20572) (in definition) includes up to 64 time-slot oriented hdlc controllers, and 2 independent serial communication controllers. additional transfer and signalling protocols such as async and ss7 (peb 3040 replacement) will be provided in dsp software. vip peb 20590 is the first (8 channel) isdn transceiver that implements multiple u pn and s/t interfaces within one device. the user can decide by programming in which mode a desired channel shall work. a total of 8 channels are provided for layer-1 subscriber or trunk line characteristic. the vip is programmed by the delic via the iom-2000 interface. vip?s eight channels are programmable in the following maximum partitioning between u pn and s/t channels: max. number of u pn and s/t channels u pn 87654 s/t01234
delic introduction preliminary data sheet 1-2 2003-08 vip-8 peb 20591 additionally to the features of the vip, the vip - 8 allows any combination of u pn s/t interface (i.e. each of the 8 channels may be programmed to s/t or u pn mode) figure 1-1 block diagram of the delic-lc iom-2 / pcm interface iom-2000 interface clocks pcm interface signaling controller jtag switch 224 x 256 ts 24 hdlc controllers p mailbox dma mailbox delic-lc serial port pcm iom-2 / pcm iom - 2000 p interface delic-lc-po.vsd
delic introduction preliminary data sheet 1-3 2003-08 figure 1-2 block diagram of the delic-pb iom-2 / pcm interface iom-2000 interface clocks pcm interface async/sync controller jtag switch hdlc controllers p mailbox dma mailbox delic-pb serial port pcm iom-2 / pcm iom - 2000 p interface program ram data ram dsp voice handling dsp emulation interface
p-tqfp-100-1 preliminary data sheet 1-4 2003-08 dsp embedded line and port interface controller delic-lc/ delic-pb peb 20570 version 2.1 cmos type package peb 20570/ peb 20571 p-tqfp-100-1 peb 20571 1.1 delic-lc key features delic-lc is optimized for line card applications: one iom-2000 interface supporting three vips i.e. up to 24 isdn channels two iom-2 (gci) ports (configurable as pcm ports) supporting up to 16isdn channels or 32 analog subscribers four pcm ports with up to 4 x 2.048 mbit/s (4 x 32 ts) or 2 x 4.096 mbit/s or 1 x 8.192 mbit/s switching matrix 224 x 256 ts (8-bit switching) 24 hdlc controllers assignable to any d- or b-channel (at 16 kbit/s or 64 kbit/s) serial communication controller: high-speed signaling channel for 2.048 mbit/s standard multiplexed and de-multiplexed p interface: siemens, intel, motorola programmable pll based master/slave clock generator, providing all system clocks from a single 16.384 mhz crystal source jtag compliant test interface single 3.3 v power supply, 5 v tolerant inputs 1.2 delic-pb key features compared to the delic-lc, having a fixed functionality, the delic-pb provides a high degree of flexibility (in terms of selected number of ports or channels). additionally it features computing power for typical dsp-oriented pbx tasks like conferencing, dtmf.. a microsoft windows based configuration tool, the configurator, enables to generate an application specific functionality. its features are mainly determined by the firmware of the integrated telecom dsp.
delic introduction preliminary data sheet 1-5 2003-08 list of maximum available features: one iom-2000 interface supporting up to three vips i.e. up to 24 isdn channels up to two iom-2 (gci) ports (also configurable as pcm ports) supporting up to 16 isdn channels or 32 analog subscribers up to four pcm ports with up to 4 x 2.048 mbit/s (4 x 32 ts) or 2 x 4.096 mbit/s or 1 x 8.192 mbit/s switching matrix 224 x 256 ts (switching of 4-/8- bit time slots) up to 32 hdlc controllers assignable to any d- or b-channel (at 16 kbit/s or 64 kbit/s) serial communication controller: high-speed signaling channel of up to 16.384 mbit/s dect synchronization support standard multiplexed and de-multiplexed p interface: siemens, intel, motorola dedicated dma support mailbox integrated dsp core oak ? + (up to 60 mips for layer 1 control, signalling and dsp- algorithms) 4 kw on-chip program memory 2 kw on-chip data memory 2 kw rom dsp work load measurement for run-time statistics, dsp alive indication on chip debugging unit serial dsp program debugging interface connected via jtag port a-/-law conversion unit programmable pll based master/slave clock generator, providing all system clocks from a single 16.384 mhz crystal source jtag compliant test interface single 3.3 v power supply, 5 v compatible inputs note: as each feature consumes system resources (dsp-performance, memory, port pins), the maximum available number of supported interfaces or hdlc channels is limited by the totally available resources. a system configurator tool helps to determine a valid configuration.
delic introduction preliminary data sheet 1-6 2003-08 1.3 logic symbol figure 1-1 logic symbol lnc or signaling interface delphi-lc peb20570 delphi-pb peb 20571 clock signals 7 9 14 5 5 27 26 delic-logic-ds.vsd iom-2000/ lnc interface 5 test interface 2 p-tqfp-100 iom-2 interfaces pcm/ lnc interfaces p interface power supply jtag interface p-tqfp-100-1
delic introduction preliminary data sheet 1-7 2003-08 1.4 typical applications the following two figures show example configurations of delic-pb line card applications for different isdn interface standards. in figure 1-2 , three vip transceiver ics are connected to the delic-pb via the new iom-2000 interface, whereas in figure 1-3 and figure 1-4 iom-2 (gci) interfaces are used. figure 1-2 delic-lc in s/t and upn line cards (up to 8 s/t and 16 upn) delic peb 20570 (peb 20571) pcm 4 x 32 ts iom-2000 signaling up to 2.048 mbit/s up to 4 x s/t 4 x upn up to 4 x s/t 4 x upn 8 x upn memory p infineon c166 vip peb 20590 vip peb 20590 vip peb 20590
delic introduction preliminary data sheet 1-8 2003-08 figure 1-3 delic-lc in uk0 line card for 16 subscribers figure 1-4 delic-pb in analog line card for 16 subscribers . . . . . . delic peb 20570 (peb 20571) iom-2 memory p infineon c166 pcm 4 x 32 ts signaling 16 x u k0 quad-u quad-u quad-u quad-u hybrid hybrid hybrid hybrid hybrid hybrid hybrid hybrid delphi-pb peb 20571 iom-2 memory p siemens c166 pcm 4 x 32 ts signaling 16 x t/r slicofi - 2 slicofi - 2 slicofi - 2 slicofi - 2 hv-slic hv-slic hv-slic iom-2 hv-slic hv-slic hv-slic hv-slic hv-slic
delic introduction preliminary data sheet 1-9 2003-08 figure 1-5 delic-pb in small pbx delic-pb peb 20571 iom-2 memory p infineon c166 vip peb 20590 iom-2000 pcm lnc 2 mbit/s for service power supply hv-slic hv-slic hv-slic hv-slic slicofi-2 slicofi-2 central office 32 x t/r 4 x u pn 2 x s 2 x t up to 32 ts
delic peb 20571 pin descriptions preliminary data sheet 2-1 2003-08 2 pin descriptions 2.1 pin diagram delic-lc (top view) figure 2-1 pin configuration delic-lc p-tqfp-100-1 50 49 44 43 42 41 48 47 46 45 40 39 34 33 31 38 37 36 35 76 77 82 83 84 85 78 79 80 81 86 87 92 93 94 95 88 89 90 91 d3 v ss ale wr / r/w rd / ds cs v dd d2 d1 d0 dreqr dreqt iack xclk dsp_frq clk_dsp v ss mode ireq tms jtck lcxd0/lcts0 ltsc0/ lrts0 ltxd0 lrxd0 trst lclk0 v dd v ss dsp_stop stat/ lcts1 dx/ ltxd1 dcl_2000/ lrts1 rxd3/ lcts3 v ss v dd v ss cmd/ lclk1 dr/ lrxd1 delic-lc peb 20570 d4 d7 d5 d6 dcxopd 30 29 28 27 26 32 96 97 98 99 100 scanmo v ss dd1 dd0 du1 du0 l1_clk v ss v dd drdy dcl fsc a4 a3 a2 a1 a6 v ss v dd a5 txd0/ltxd2 v dd v ss txd3/lclk3 pfs txd1/ltxd3 tsc2 txd2/lclk2 tsc3 pdc resind v ssa v ssa v dda v dda refclk v ss v ssa v dd 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 tdo tdi/ scanen v dd rxd2/ lcts2 rxd1/lrxd3 rxd0/lrxd2 1 2 3 4 5 6 7 8 9 10 11 1213 14 15 16 1718 19 20 21 22 23 2425 reset clkout v ss v dd a0 v dd clk16-xi clk16-xo v dda tsc1 / lrts3 tsc0 / lrts2
delic peb 20571 pin descriptions preliminary data sheet 2-2 2003-08 2.2 pin diagram delic-pb (top view) figure 2-2 pin configuration delic-pb p-tqfp-100-1 50 49 44 43 42 41 48 47 46 45 40 39 34 33 31 38 37 36 35 76 77 82 83 84 85 78 79 80 81 86 87 92 93 94 95 88 89 90 91 d3 v ss ale wr / r/w rd / ds cs v dd d2 d1 d0 dreqr dreqt iack xclk dsp_frq clk_dsp v ss mode ireq tms jtck lcxd0/lcts0 ltsc0/ lrts0 ltxd0 lrxd0 trst lclk0 v dd v ss dsp_stop stat/ lcxd1/lcts1 dx/ ltxd1 dcl_2000/ ltsc1/lrts1 rxd3/ lcxd3/lcts3 v ss v dd v ss cmd/ lclk1 dr/ lrxd1 delic-pb peb 20571 d4 d7 d5 d6 dcxopd 30 29 28 27 26 32 96 97 98 99 100 scanmo v dd dd1 dd0 du1 du0 l1_clk v ss v dd drdy dcl fsc a4/dack a3 a2 a1 a6 v ss v dd a5 txd0/ltxd2 tsc1 / ltsc3 /lrts3 v dd v ss txd3/lclk3 pfs txd1/ltxd3 tsc2 txd2/lclk2 tsc3 pdc resind v ssa v ssa v dda v dda refclk v ss v ssa v dd 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 tdo tdi/ scanen v dd rxd2/ lcxd2/lcts2 rxd1/lrxd3 rxd0/lrxd2 tsc0 / ltsc2 /lrts2 123456 7 8 9 10 11 1213 14 15 16 1718 19 20 21 22 23 2425 reset clkout v ss v dd a0 v dd clk16-xi clk16-xo v dda
delic peb 20571 pin descriptions preliminary data sheet 2-3 2003-08 2.3 pin definitions and functions for delic-lc note: the column ?during reset? refers to the time period that starts with activation of reset input and ends with the deactivation of the resind output. during this period, the delic?s strap pins (refer to table 2-19 ) may be driven by external pull- down or pull-up resistors to define delic? s configuration. if external pull-down or pull-up resistors are not connected to the strap pins, the value of each strap pin during reset will be determined by an internal pull-up or pull-down resistor, according to the default strap value of each pin. the user must ensure that connected circuits do not influence the sampling of the strap pins during reset. the column ?after reset? describes the behavior of every pin, from the deactivation of the resind output until the delic?s registers are programmed. table 2-1 iom ? -2 interface pins (delic-lc) pin no. symbol in (i) out(o) during reset after reset function 39 fsc o o o frame synchronization clock (8 khz) used for both the iom-2 and the iom- 2000 interface 40 dcl o test- strap (3), (internal pull-up), refer to table 2-19 o iom-2 data clock 2.048 mhz or 4.096 mhz 43 dd0 o(od) high z high z data downstream iom-2 interface channel0 44 dd1 o(od) high z high z data downstream iom-2 interface channel1 41 du0 i i i data upstream iom-2 interface channel 0 42 du1 i i i data upstream iom-2 interface channel 1 45 drdy i i i d- channel ready stop/go information for d-channel control on s/t interface in lt-t. affects only iom-2 port 0. drdy = 1 means go drdy = 0 means stop
delic peb 20571 pin descriptions preliminary data sheet 2-4 2003-08 table 2-2 iom-2000 interface / lnc port 1 (delic-lc) pin no. symbol in (i) out (o) during reset after reset function 70 dcl_2000 / lrts1 o o o o iom-2000 data clock 3.072, 6.144 or 12.288 mhz ?request-to-send? functionality (async mode) 69 dx / ltxd1 o o (od) high z high z data transmit transmits iom-2000 data to vip lnc transmit serial data port 1 (async mode). 68 dr / lrxd1 i i i i data receive receives iom-2000 data from vip lnc receive serial data port 1 (async mode). 67 cmd / lclk1 o i/o high z high z iom-2000 command transmits delic commands to vip. lnc clock port 1. when configured as output may be driven at the following frequencies: 2.048 mhz, 4.096 mhz, 8.192 mhz, 16.384 mhz 64 stat / lcts1 i i i i iom-2000 status receives status information from vip. lnc1 clear to send ?clear-to-send? functionality (async mode)
delic peb 20571 pin descriptions preliminary data sheet 2-5 2003-08 table 2-3 lnc port 0 (delic-lc) pin no. symbol in (i) out (o) during reset after reset function 62 lrxd0 i i i lnc receive serial data port 0 (hdlc and async mode). 61 ltxd0 o (od) high z high z lnc transmit serial data port 0 (hdlc and async mode). 60 ltsc0 / lrts0 o pll- bypass ? strap. internal pull-up refer to page 2- 28 h lnc0 tristate control / request to send 2 modes per s/w selectable: 1) txd output is valid (hdlc mode). supplies a control signal for an external driver. (?low? when the corresponding txd-output is valid). 2) ?request-to-send? functionality (async mode) 59 lcxd0 / lcts0 i i i lnc0 collision data / clear to send 2 modes per s/w selectable: 1) collision data (hdlc mode). 2) ?clear-to-send? functionality (async mode) 56 lclk0 i/o i i lnc clock port 0 when configured as output may be driven at the following frequencies: 2.048 mhz, 4.096 mhz, 8.192 mhz, 16.384 mhz
delic peb 20571 pin descriptions preliminary data sheet 2-6 2003-08 table 2-4 microprocessor bus interface pins (delic-lc) pin no. symbol in (i) out (o) during reset after reset function 25 24 23 22 21 18 17 16 d7 d6 d5 d4 d3 d2 d1 d0 i/o the direction of these pins depends on the value of the following pins: cs , rd /ds , wr / r/w and mode data bus note: when operated in address/data multiplex mode, this bus is used as a multiplexed ad bus. the address pins are externally connected to the ad bus. 38 35 34 33 32 31 30 a6 a5 a4 a3 a2 a1 a0 i i i address bus (bits 6 ... 0) note: when operated in address/data multiplex mode, this bus is used as a multiplexed ad bus. the data pins are externally connected to the ad bus. 11 dreqr o clock master strap (internal pull-down), refer to table 2-19 l strap pin 10 dreqt o emul- ation boot strap (internal pull-down), refer to table 2-19 l strap pin 12 cs ii ichip select a "low" on this line selects all registers for read/write operations.
delic peb 20571 pin descriptions preliminary data sheet 2-7 2003-08 13 wr / r/w i i i write (intel/siemens mode) indicates a write access. read/write (motorola mode) indicates the direction of the data transfer 14 rd / ds i i i read (intel/siemens mode) indicates a read access. data strobe (motorola mode) during a read cycle, ds indicates that the delic should place valid data on the bus. during a write access, ds indicates that valid data is on the bus. 15 ale i i i address latch enable controls the on-chip address latch in multiplexed bus mode. while ale is ?high?, the latch is transparent. the falling edge latches the current address. ale is also evaluated to determine the bus mode (?low?=multiplexed, ?high?=demultiplexed) 7 mode i i i bus mode selection selects the p bus mode (?low?=intel/infineon, ?high?=motorola) 6ireqo (od) high z (od) high z (od) interrupt request is programmable to push/pull (active high or low) or open- drain. this signal is activated when the delic requests a p interrupt. when operated in open drain mode, multiple interrupt sources may be connected. 5iack i i i interrupt acknowledge table 2-4 microprocessor bus interface pins (delic-lc) (continued) pin no. symbol in (i) out (o) during reset after reset function
delic peb 20571 pin descriptions preliminary data sheet 2-8 2003-08 29 reset i i i system reset delic is forced to go into reset state. 89 resind o o o reset indication indicates that the delic is executing a reset. the delic remains in reset state for at least 500 s after the termination of the reset pulse. table 2-5 pcm interface ports 0 ... 3 / lnc ports 2 ... 3 (delic-lc) pin no. symbol in (i) out (o) during reset after reset function 87 pfs i/o i i pcm frame synchronization clock. 8 khz/4 khz when input or 8 khz when output. note: when pfs is configured as 4 khz input, pdc configuration is restricted to 2.048 mhz input. 88 pdc i/o i i pcm data clock (input or output) 2.048 mhz, 4.096 mhz, 8.192 mhz, 16.384 mhz 76 rxd0 / lrxd2 i i i i pcm receive data port 0 lnc receive serial data port 2 (async mode) 78 txd0 / ltxd2 o o(od) high z high z pcm transmit data port 0 lnc transmit serial data port 2 async mode) table 2-4 microprocessor bus interface pins (delic-lc) (continued) pin no. symbol in (i) out (o) during reset after reset function
delic peb 20571 pin descriptions preliminary data sheet 2-9 2003-08 77 tsc0 / lrts2 o o reset counter bypass ? strap internal pull-up refer to page 2- 28 h pcm tristate control port 0 supplies a control signal for an external driver (?low? when the corresponding txd- output is valid). lnc2 tristate control / request to send ?request-to-send? functionality (async mode) 74 rxd2 / lcts2 i i i i pcm receive data port 2 lnc2 ?clear-to-send? functionality (async mode) 82 txd2 / lclk2 o i/o weak low weak low pcm transmit data port 2 lnc external clock port 2 when configured as output may be driven at the following frequencies: 2.048 mhz, 4.096 mhz, 8.192 mhz, 16.384 mhz 81 tsc2 o test(1) strap refer to page 2- 28 h pcm tristate control port 2 supplies a control signal for an external driver (?low? when the corresponding txd- output is valid). 75 rxd1 / lrxd3 i i i i pcm receive data port 1 lnc receive serial data port 3 (async mode) 80 txd1 / ltxd3 o o(od) high z high z pcm transmit data port 1 lnc transmit serial data port 3 (async mode) table 2-5 pcm interface ports 0 ... 3 / lnc ports 2 ... 3 (delic-lc) (continued) pin no. symbol in (i) out (o) during reset after reset function
delic peb 20571 pin descriptions preliminary data sheet 2-10 2003-08 79 tsc1 / lrts3 opll power- down strap internal pull-up refer to page 2- 28 h pcm tristate control port 1 supplies a control signal for an external driver (?low? when the corresponding txd- output is valid). lnc3 request to send ?request-to-send? functionality (async mode) 71 rxd3 / lcts3 i i i i pcm receive data port 3 lnc3 ?clear-to-send? functionality (async mode) 86 txd3 / lclk3 o i/o weak low weak low pcm transmit data port 3 lnc external clock port 3 when configured as output may be driven at the following frequencies: 2.048 mhz, 4.096 mhz, 8.192 mhz, 16.384 mhz 83 tsc3 o test(1) strap refer to page 2- 28 h pcm tristate control port 3 supplies a control signal for an external driver (?low? when the corresponding txd output is valid). table 2-5 pcm interface ports 0 ... 3 / lnc ports 2 ... 3 (delic-lc) (continued) pin no. symbol in (i) out (o) during reset after reset function
delic peb 20571 pin descriptions preliminary data sheet 2-11 2003-08 . table 2-6 clock generator pins (delic-lc) (additionally to iom/pcm clocks) pin no. symbol in (i) out (o) during reset after reset function 94 clk16-xi i i i 16.384 mhz external crystal input 95 clk16-xo o o o 16.384 mhz external crystal output 1 dcxopd i i i dcxo power down and bypass activating this input powers down the on-chip dcxo pll. the input clk16-xi is used directly as the internal 16.384 mhz clock, and the oscillator and the shaper are bypassed. required for testing; during normal operation this input should be permanently low (?0?). 2 clk_dsp i i i external dsp clock provides a dsp clock other than 61.44 mhz from an external oscillator. 3 dsp_frq i i i dsp operational frequency selection (e.g. for test purpose) 0: the dsp is clocked internally at 61.44 mhz 1: the dsp clock is driven by the clk_dsp input pin 48 l1_clk o o o layer-1 clock 15.36 mhz or 7.68 mhz 28 clkout o o o general purpose clock output 2.048 mhz, 4.096 mhz, 8.192 mhz, 15.36 mhz or 16.384 mhz 4 xclk i i i external reference clock synchronization input from layer-1 ics (8 khz, 512 khz or 1.536 mhz) this pin is connected to the vip?s refclk output at 1.536 mhz. 90 refclk i/o i i reference clock input: synchronization of delic clock system output: used to drive a fraction of xclk to the system clock master (8 khz or 512 khz programmable)
delic peb 20571 pin descriptions preliminary data sheet 2-12 2003-08 table 2-7 power supply pins (delic-lc) pin no. symbol in (i) out (o) during reset after reset function 8 19 26 36 46 57 65 72 84 91 v dd i i i power supply 3.3 v used for core logic and interfaces in pure 3.3 v environment 9 20 27 37 47 49 58 66 73 85 92 v ss i i i digital ground (0 v) 96 99 100 v dda i i i power supply 3.3 v analog logic used for dcxo and pll 93 97 98 v ssa i i i analog ground used for dcxo and pll
delic peb 20571 pin descriptions preliminary data sheet 2-13 2003-08 table 2-8 jtag and emulation interface pins (delic-lc) pin no. symbol in (i) out (o) during reset after reset function used for boundary scan according to ieee 1149.1 54 jtck i i i jtag test clock provides the clock for jtag test logic. used also for serial emulation interface. 53 tms i i i test mode select a ?0? to ?1? transition on this pin is required to step through the tap controller state machine. 52 tdi / scanen i i i test data input in the appropriate tap controller state test data or a instruction is shifted in via this line. used also for serial emulation interface. note: this pin must not be driven to low on the board during reset and operation to ensure functioning of delic scan enable when both scanmo and scanen are asserted, the full-scan tests of delic are activated. not used during normal operation. 51 tdo o o o test data output in the appropriate tap controller state test data or an instruction is shifted out via this line. used also for serial emulation interface.
delic peb 20571 pin descriptions preliminary data sheet 2-14 2003-08 55 trst iiitest reset provides an asynchronous reset to the tap controller state machine. 63 dsp_sto p o boot strap (intern al pull- down) refer to table 2-19 o dsp stop pin stops external logic during breakpoints. activated when a stop to the dsp is issued. table 2-9 test interface pins (delic-lc) pin no. symbol in (i) out (o) during reset after reset function 50 scanmo i i i scan mode if driven to ?1? during device tests, tdi input is used as enable for full scan tests of the delic. scanmo should be tied to gnd during normal operation. table 2-8 jtag and emulation interface pins (delic-lc) (continued) pin no. symbol in (i) out (o) during reset after reset function
delic peb 20571 pin descriptions preliminary data sheet 2-15 2003-08 2.4 pin definitions and functions for delic-pb note: the column ?during reset? refers to the time period that starts with activation of reset input and ends with the deactivation of the resind output. during this period, the delic?s strap pins (refer to table 2-19 ) may be driven by external pull- down or pull-up resistors to define delic? s configuration. if external pull-down or pull-up resistors are not connected to the strap pins, the value of each strap pin during reset will be determined by an internal pull-up or pull-down resistor, according to the default strap value of each pin. the user must ensure that connected circuits do not influence the sampling of the strap pins during reset. the column ?after reset? describes the behavior of every pin, from the deactivation of the resind output until the delic?s registers are programmed. table 2-10 iom ? -2 interface pins (delic-pb) pin no. symbol in (i) out(o) during reset after reset function 39 fsc o o o frame synchronization clock (8 khz) used for both the iom-2 and the iom- 2000 interface 40 dcl o test- strap (3), (internal pull-up), refer to table 2-19 o iom-2 data clock 2.048 mhz or 4.096 mhz 43 dd0 o(od) high z high z data downstream iom-2 interface channel0 44 dd1 o(od) high z high z data downstream iom-2 interface channel1 41 du0 i i i data upstream iom-2 interface channel 0 42 du1 i i i data upstream iom-2 interface channel 1 45 drdy i i i d- channel ready stop/go information for d-channel control on s/t interface in lt-t. affects only iom-2 port 0. drdy = 1 means go drdy = 0 means stop
delic peb 20571 pin descriptions preliminary data sheet 2-16 2003-08 table 2-11 iom-2000 interface / lnc port 1 (delic-pb) pin no. symbol in (i) out (o) during reset after reset function 70 dcl_2000 / ltsc1/ lrts1 o o o o iom-2000 data clock 3.072, 6.144 or 12.288 mhz lnc1 tristate control /request to send 2 modes per s/w selectable: 1) txd output is valid (hdlc mode). supplies a control signal for an external driver. (?low? when the corresponding txd-output is valid). 2) ?request-to-send? functionality (async mode) 69 dx / ltxd1 o o (od) high z high z data transmit transmits iom-2000 data to vip lnc transmit serial data port 1 (hdlc and async mode). 68 dr / lrxd1 i i i i data receive receives iom-2000 data from vip lnc receive serial data port 1 (hdlc and async mode). 67 cmd / lclk1 o i/o high z high z iom-2000 command transmits delic commands to vip. lnc clock port 1. when configured as output may be driven at the following frequencies: 2.048 mhz, 4.096 mhz, 8.192 mhz, 16.384 mhz 64 stat / lcxd1/ lcts1 i i i i iom-2000 status receives status information from vip. lnc1 collision data / clear to send 1) collision data (hdlc mode). 2) ?clear-to-send? functionality (async mode)
delic peb 20571 pin descriptions preliminary data sheet 2-17 2003-08 table 2-12 lnc port 0 (delic-pb) pin no. symbol in (i) out (o) during reset after reset function 62 lrxd0 i i i lnc receive serial data port 0 (hdlc and async mode). 61 ltxd0 o (od) high z high z lnc transmit serial data port 0 (hdlc and async mode). 60 ltsc0 / lrts0 o pll- bypass ? strap. internal pull-up refer to page 2- 28 h lnc0 tristate control / request to send 2 modes per s/w selectable: 1) txd output is valid (hdlc mode). supplies a control signal for an external driver. (?low? when the corresponding txd-output is valid). 2) ?request-to-send? functionality (async mode) 59 lcxd0 / lcts0 i i i lnc0 collision data / clear to send 2 modes per s/w selectable: 1) collision data (hdlc mode). 2) ?clear-to-send? functionality (async mode) 56 lclk0 i/o i i lnc clock port 0 when configured as output may be driven at the following frequencies: 2.048 mhz, 4.096 mhz, 8.192 mhz, 16.384 mhz
delic peb 20571 pin descriptions preliminary data sheet 2-18 2003-08 table 2-13 microprocessor bus interface pins (delic-pb) pin no. symbol in (i) out (o) during reset after reset function 25 24 23 22 21 18 17 16 d7 d6 d5 d4 d3 d2 d1 d0 i/o the direction of these pins depends on the value of the following pins: cs , rd /ds , wr / r/w and mode data bus note: when operated in address/data multiplex mode, this bus is used as a multiplexed ad bus. the address pins are externally connected to the ad bus. 38 35 33 32 31 30 a6 a5 a3 a2 a1 a0 i i i address bus (bits 6 ... 0 except bit 4) note: when operated in address/data multiplex mode, this bus is used as a multiplexed ad bus. the data pins are externally connected to the ad bus. note: in non-dma mode dack /a4 input pin should be connected to a4 of the p address-bus. in dma mode a4 is internally connected to ?0?. 34 a4 dack / i i i dma acknowledge bit 4 of the address bus, when the delic is configured to non-dma mode. note: in dma mode a4 is internally connected to ?0?. 11 dreqr o clock master strap (internal pull-down), refer to table 2-19 l dma request for receive direction note: may be configured to active high or active low (the default is active high)
delic peb 20571 pin descriptions preliminary data sheet 2-19 2003-08 10 dreqt o emul- ation boot strap (internal pull-down), refer to table 2-19 l dma request for transmit direction note: may be configured to active high or active low (the default is active high) 12 cs ii ichip select a "low" on this line selects all registers for read/write operations. 13 wr / r/w i i i write (intel/siemens mode) indicates a write access. read/write (motorola mode) indicates the direction of the data transfer 14 rd / ds i i i read (intel/siemens mode) indicates a read access. data strobe (motorola mode) during a read cycle, ds indicates that the delic should place valid data on the bus. during a write access, ds indicates that valid data is on the bus. 15 ale i i i address latch enable controls the on-chip address latch in multiplexed bus mode. while ale is ?high?, the latch is transparent. the falling edge latches the current address. ale is also evaluated to determine the bus mode (?low?=multiplexed, ?high?=demultiplexed) 7 mode i i i bus mode selection selects the p bus mode (?low?=intel/infineon, ?high?=motorola) table 2-13 microprocessor bus interface pins (delic-pb) (continued) pin no. symbol in (i) out (o) during reset after reset function
delic peb 20571 pin descriptions preliminary data sheet 2-20 2003-08 6ireqo (od) high z (od) high z (od) interrupt request is programmable to push/pull (active high or low) or open- drain. this signal is activated when the delic requests a p interrupt. when operated in open drain mode, multiple interrupt sources may be connected. 5iack i i i interrupt acknowledge 29 reset i i i system reset delic is forced to go into reset state. 89 resind o o o reset indication indicates that the delic is executing a reset. the delic remains in reset state for at least 500 s after the termination of the reset pulse. table 2-14 pcm interface ports 0 ... 3 / lnc ports 2 ... 3 (delic-pb) pin no. symbol in (i) out (o) during reset after reset function 87 pfs i/o i i pcm frame synchronization clock. 8 khz/4 khz when input or 8 khz when output. note: when pfs is configured as 4 khz input, pdc configuration is restricted to 2.048 mhz input. 88 pdc i/o i i pcm data clock (input or output) 2.048 mhz, 4.096 mhz, 8.192 mhz, 16.384 mhz 76 rxd0 / lrxd2 i i i i pcm receive data port 0 lnc receive serial data port 2 (hdlc and async mode) 78 txd0 / ltxd2 o o(od) high z high z pcm transmit data port 0 lnc transmit serial data port 2 (hdlc and async mode) table 2-13 microprocessor bus interface pins (delic-pb) (continued) pin no. symbol in (i) out (o) during reset after reset function
delic peb 20571 pin descriptions preliminary data sheet 2-21 2003-08 77 tsc0 / ltsc2 / lrts2 o o reset counter bypass ? strap internal pull-up refer to page 2- 28 h pcm tristate control port 0 supplies a control signal for an external driver (?low? when the corresponding txd- output is valid). lnc2 tristate control / request to send 2 modes per s/w selectable: 1) txd output is valid (hdlc mode). supplies a control signal for an external driver. (?low? when the corresponding txd- output is valid). 2) ?request-to-send? functionality (async mode) 74 rxd2 / lcxd2/ lcts2 i i i i pcm receive data port 2 lnc2 collision data 2 modes per s/w selectable: 1) collision data (in hdlc mode). 2) ?clear-to-send? functionality (async mode) 82 txd2 / lclk2 o i/o weak low weak low pcm transmit data port 2 lnc external clock port 2 when configured as output may be driven at the following frequencies: 2.048 mhz, 4.096 mhz, 8.192 mhz, 16.384 mhz 81 tsc2 o test(1) strap refer to page 2- 28 h pcm tristate control port 2 supplies a control signal for an external driver (?low? when the corresponding txd- output is valid). table 2-14 pcm interface ports 0 ... 3 / lnc ports 2 ... 3 (delic-pb) (continued) pin no. symbol in (i) out (o) during reset after reset function
delic peb 20571 pin descriptions preliminary data sheet 2-22 2003-08 75 rxd1 / lrxd3 i i i i pcm receive data port 1 lnc receive serial data port 3 (hdlc and async mode) 80 txd1 / ltxd3 o o(od) high z high z pcm transmit data port 1 lnc transmit serial data port 3 (hdlc and async mode) 79 tsc1 / ltsc3 / lrts3 opll power- down strap internal pull-up refer to page 2- 28 h pcm tristate control port 1 supplies a control signal for an external driver (?low? when the corresponding txd- output is valid). lnc3 tristate control / request to send 2 modes per s/w selectable: 1) txd output is valid (hdlc mode). supplies a control signal for an external driver. (?low? when the corresponding txd- output is valid). 2) ?request-to-send? functionality (async mode) 71 rxd3 / lcxd3/ lcts3 i i i i pcm receive data port 3 lnc3 collision data 2 modes per s/w selectable: 1) collision data (hdlc mode). 2) ?clear-to-send? functionality (async mode) table 2-14 pcm interface ports 0 ... 3 / lnc ports 2 ... 3 (delic-pb) (continued) pin no. symbol in (i) out (o) during reset after reset function
delic peb 20571 pin descriptions preliminary data sheet 2-23 2003-08 86 txd3 / lclk3 o i/o weak low weak low pcm transmit data port 3 lnc external clock port 3 when configured as output may be driven at the following frequencies: 2.048 mhz, 4.096 mhz, 8.192 mhz, 16.384 mhz 83 tsc3 o test(1) strap refer to page 2- 28 h pcm tristate control port 3 supplies a control signal for an external driver (?low? when the corresponding txd output is valid). table 2-14 pcm interface ports 0 ... 3 / lnc ports 2 ... 3 (delic-pb) (continued) pin no. symbol in (i) out (o) during reset after reset function
delic peb 20571 pin descriptions preliminary data sheet 2-24 2003-08 . table 2-15 clock generator pins (delic-pb) (additionally to iom/pcm clocks) pin no. symbol in (i) out (o) during reset after reset function 94 clk16-xi i i i 16.384 mhz external crystal input 95 clk16-xo o o o 16.384 mhz external crystal output 1 dcxopd i i i dcxo power down and bypass activating this input powers down the on-chip dcxo pll. the input clk16-xi is used directly as the internal 16.384 mhz clock, and the oscillator and the shaper are bypassed. required for testing; during normal operation this input should be permanently low (?0?). 2 clk_dsp i i i external dsp clock provides a dsp clock other than 61.44 mhz from an external oscillator. 3 dsp_frq i i i dsp operational frequency selection (e.g. for test purpose) 0: the dsp is clocked internally at 61.44 mhz 1: the dsp clock is driven by the clk_dsp input pin 48 l1_clk o o o layer-1 clock 15.36 mhz or 7.68 mhz 28 clkout o o o general purpose clock output 2.048 mhz, 4.096 mhz, 8.192 mhz, 15.36 mhz or 16.384 mhz 4 xclk i i i external reference clock synchronization input from layer-1 ics (8 khz, 512 khz or 1.536 mhz) this pin is connected to the vip?s refclk output at 1.536 mhz. 90 refclk i/o i i reference clock input: synchronization of delic clock system output: used to drive a fraction of xclk to the system clock master (8 khz or 512 khz programmable)
delic peb 20571 pin descriptions preliminary data sheet 2-25 2003-08 table 2-16 power supply pins (delic-pb) pin no. symbol in (i) out (o) during reset after reset function 8 19 26 36 46 49 57 65 72 84 91 v dd i i i power supply 3.3 v used for core logic and interfaces in pure 3.3 v environment 9 20 27 37 47 58 66 73 85 92 v ss i i i digital ground (0 v) 96 99 100 v dda i i i power supply 3.3 v analog logic used for dcxo and pll 93 97 98 v ssa i i i analog ground used for dcxo and pll
delic peb 20571 pin descriptions preliminary data sheet 2-26 2003-08 table 2-17 jtag and emulation interface pins (delic-pb) pin no. symbol in (i) out (o) during reset after reset function used for boundary scan according to ieee 1149.1 54 jtck i i i jtag test clock provides the clock for jtag test logic. used also for serial emulation interface. 53 tms i i i test mode select a ?0? to ?1? transition on this pin is required to step through the tap controller state machine. 52 tdi / scanen i i i test data input in the appropriate tap controller state test data or a instruction is shifted in via this line. used also for serial emulation interface. note: this pin must not be driven to low on the board during reset and operation to ensure functioning of delic scan enable when both scanmo and scanen are asserted, the full-scan tests of delic are activated. not used during normal operation. 51 tdo o o o test data output in the appropriate tap controller state test data or an instruction is shifted out via this line. used also for serial emulation interface.
delic peb 20571 pin descriptions preliminary data sheet 2-27 2003-08 55 trst iiitest reset provides an asynchronous reset to the tap controller state machine. 63 dsp_sto p o boot strap (intern al pull- down) refer to table 2-19 o dsp stop pin stops external logic during breakpoints. activated when a stop to the dsp is issued. table 2-18 test interface pins (delic-pb) pin no. symbol in (i) out (o) during reset after reset function 50 scanmo i i i scan mode if driven to ?1? during device tests, tdi input is used as enable for full scan tests of the delic. scanmo should be tied to gnd during normal operation. table 2-17 jtag and emulation interface pins (delic-pb) (continued) pin no. symbol in (i) out (o) during reset after reset function
delic peb 20571 pin descriptions preliminary data sheet 2-28 2003-08 2.5 strap pin definitions table 2-19 strap pins (evaluated during reset) pin no. strap name strap function dreqr (11) clock master 0: (default) 1: clock slave pdc and pfs are used as inputs. pdc = 2.048 mhz pfs = 4 khz clock master pdc and pfs are used as outputs. pdc = 2.048 mhz pfs = 8 khz dsp_stop (63) boot 0: (default) 1: the dsp starts running from address fffe h , and executes the p boot routine. the dsp starts running directly from address 0000 h . the boot routine is not executed. dcl (40): tsc3 (83): tsc2 (81) test (3:1) 111 or 110: (default) regular work mode 101 test mode 1 100 test mode 2 011 test mode 3 010 test mode 4 001 test mode 5 dreqt (10) emulation boot 0: (default) 1: after reset the boot-routine loads the program ram via the p-interface (via the general mail- box). after reset the boot-routine loads the program ram via the cdi mail-box (via the jtag interface). ltsc (60) pll bypass 0: 1: (default) dsp_clk input pin (the dsp fall-back clock) is used as source for the 61 mhz clock division chain. (only for testing). the pll output is used as the source for the 61 mhz clock division chain.
delic peb 20571 pin descriptions preliminary data sheet 2-29 2003-08 note: when the strap pins are not driven externally during reset, they are driven by internal pull-ups/pull-downs. to reduce power consumption, the internal pull-up/ pull-down resistors are connected only during activated reset input. to ensure the default value of the straps, the pins must not be driven during reset. in case of fixed external pull-up/pull-down, a pull-up/pull-down resistance of 10 k ? +/-10% is recommended. tsc1 (79) pll power down 0: 1: (default) the pll is powered-down. (for iddq tests) the pll is on. tsc0 (77) reset counter bypass 0: 1: (default) the reset-counter is bypassed, thus the internal reset is the filtered reset. the internal reset lasts 1-2 16 mhz cycles after a deactivation of reset . the internal reset lasts 4-5 8 khz cycles (> 500 s) after a deactivation of reset table 2-19 strap pins (evaluated during reset) (continued)
delic interface description preliminary data sheet 3-1 2003-08 3 interface description 3.1 overview of interfaces the delic provides the following system interfaces: iom-2000 interface a new serial layer 1 interface driving up to three vip/ vip8 (v ersatile i sdn p ort, peb 20590/ peb 20591). each vip provides eight 2b+d isdn channels, which can be programmed via iom-2000 to s/t mode or u pn mode. iom-2 (gci) interface two standard iom-2 (gci) ports with eight 2b+d isdn channels each, at a data rate of up to 2 x 2.048 mbit/s. they can be combined to a 4.096 mbit/s highway. pcm interface four standard master/slave pcm interfaces with up to 32 time slots each, at a data rate of up to 4 x 2.048 mbit/s. they can be combined to two 4.096 mbit/s highways or one 8.192 mbit/s highway. additionally, 128 time slots of 256 time slots per 8 khz frame can be transmitted at a rate of 16.384 mbit/s. serial communication interface (ghdlc) an asynchronous serial port supporting hdlc formatted data frames at a data rate of up to 16.384 mbit/s. microprocessor interface a standard 8-bit multiplexed/de-multiplexed p interface, compatible to intel/siemens (e.g. 80386ex, c166) and motorola (e.g. 68340, 801) bus systems. it includes two separate mailboxes, one for normal data transfer, and one for fast dma transfers. jtag boundary scan test interface delic provides a standard test interface according to ieee 1149.1. the 4-bit tap controller has an own reset input. the jtag pins tdi, tdo and jtck may also be used as interface for dsp emulation.
delic interface description preliminary data sheet 3-2 2003-08 3.2 iom-2000 interface 3.2.1 overview the iom-2000 interface represents a new concept for connecting isdn layer-1 devices to the delic. the transceiver unit (transiu) and the dsp perform the layer-1 protocol, which enables flexible and efficient operation of the transceiver ic (vip/ vip8). vip/ vip8 supports two types of isdn interfaces: 2-wire (ping-pong) u pn interfaces and 4-wire s/t interfaces. for detailed description please refer to vip/ vip8 data sheet. the iom-2000 interface consists of the following signals: frame synchronization: iom-2000 uses the same 8 khz fsc as the iom-2 ports. data interface: data is transmitted via dx line from delic to vip with dcl_2000 rising edge. data is received via dr line from vip to delic, sampled with dcl_2000 falling edge. command/status interface: configuration and control information of vip?s layer-1 transceivers is exchanged via cmd and stat lines. data/command clock: data and commands for one vip are transmitted at 3.072 mhz. when delic drives 2 or 3 vips, the transmission rate is increased. reference clock: in lt-t mode, the vip provides a reference clock synchronized to the exchange. in lt-s or u pn mode, delic is always the clock master to vip. figure 3-1 overview of iom-2000 interface structure (example with one vip) bit 1 bit 0 bit 0 s/t: u pn : dx / dr: data transmit / receive in s/t mode f=3.072 mhz (2 x 8 x 192 kbit/s) data transmit / receive for u pn mode f=3.072 mhz (8 x 384 kbit/s) channel_0 channel_7 fsc dcl_2000 dx cmd dr stat vip delic . . . peb 20590 peb 20570 data ctrl data
delic interface description preliminary data sheet 3-3 2003-08 3.2.2 iom-2000 frame structure 3.2.2.1 data interface on the isdn line side of the vip, data is ternary coded. since the vip contains logic to detect the level of the signal, only the data value is transferred via iom-2000 to delic. u pn mode in u pn mode, only data is sent via the iom-2000 data interface. s/t mode in s/t mode, data and control information is sent via iom-2000 data interface. every data bit has a control bit associated with it. thus, for each s/t line signal, 2 bits are transferred via dx and dr. bit0 is assigned to the user data, and bit1 carries control information. note: ?data? is always transmitted prior to ?ctrl? via dx/dr lines (refer to figure 3-2 ). table 3-1 control bits in s/t mode on dr line ctrl (bit1) data (bit0) function 0 0 logical ?0? received on line interface 0 1 logical ?1? received on line interface 1 0 received e-bit = inverted transmitted d-bit (e=d ) (lt-t only) 1 1 f-bit (framing) received; indicates the start of the s frame table 3-2 control bits in s/t mode on dx line ctrl (bit1) data (bit0) function 0 0 logical ?0? transmitted on line interface 0 1 logical ?1? transmitted on line interface 1 0 not used 1 1 f-bit (framing) transmitted; indicates the start of the s frame
delic interface description preliminary data sheet 3-4 2003-08 figure 3-2 iom-2000 data sequence (1 vip with 8 channels) note: 1. data transfer on iom-2000 interface always starts with the msb (related to b channels), whereas cmd and stat bits transfer always starts with lsb (bit 0) of any register 2. all registers follow the intel structure (lsb=2 0 , msb=2 31 ) 3. unused bits are don?t care (?x?) 4. the order of reception or transmission of each vip channel is always channel 0 to channel 7. a freely programmable channel assignment of multiple vips on iom-2000 (e.g., ch0 of vip_0, ch1 of vip_0, ch0 of vip_1, ch2 of vip_0, ...) is not possible. fsc dcl ch0 bit0 ch1 bit0 (data) dx/dr 125 s 3.072 mhz lt-s mode: u pn mode: ch7 bit 23 (ctrl) f-bit ch0 bit1 ch1 bit0 (ctrl) ch1 bit1 (data) ch7 bit1 (data) ch1,3,5,7 in s mode (lt-s) ch0,2,4,6 in u pn mode ch7 bit0 (data) ch7 bit0 (ctrl) ch0 bit2 data data ctrl ch2 bit2 ch2 bit1 ch2 bit0 ch6 bit37 last bit of u pn frame last bit of lt-s frame
delic interface description preliminary data sheet 3-5 2003-08 figure 3-3 iom-2000 data order (3 vips with 24 channels) receive data channel shift in receive direction (dr), data of all iom-2000 channels (ch0...7 if one vip is used, ch0 ... ch23 if three vips are used) is shifted by 2 channels with respect to the transmitted data channels (dx), assuming a start of transmission of ch0 bit0 with the fsc signal. delic is transmitting ch0, while receiving ch2 via dr the same time, etc. dx ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 ch0 dr ch2 ch3 ch4 ch5 ch6 ch7 ch0 ch1 ch2 fsc dcl ch0 bit0 dx/dr 125 s 12.288 mhz f-bit ch24 bit0 (example for 24 channels in u pn mode) ch0 bit37 ch31 bit0 ch23 bit0 not used (don?t care) ch0 bit1 ch24 bit1 ch31 bit1 ch23 bit1 not used (don?t care) ch23 bit37 ch24 bit37 ch31 bit37 not used
delic interface description preliminary data sheet 3-6 2003-08 3.2.2.2 command and status interface the cmd and stat lines are the configuration and control interface between delic and vip. the bit streams are partitioned into 32-bit words carrying information dedicated to the vips (cmd_0 / stat_0) followed by information dedicated to the individual channels of the same vip (cmd_0_0 ... cmd_2_7 or stat_0_0 ... stat_2_7). note: as opposed to data, command and status bits are sent channel-wise, starting with channel_0. the transmission clock is the same as the dr/dx data clock. figure 3-4 iom-2000 cmd/stat handling (1 vip with 8 channels) note: the position of each vip within the iom-2000 frame is programmable by two vip pins (vip_adr0, vip_adr1) to iom-2000 channels 0..7, 8..15 or 16..23. figure 3-5 iom-2000 command/status sequence (3 vips with 24 channels) fsc dcl cmd s_0c6 s_0c0 s_0c7 stat 0 1 2 31 s_0 status bits of vip_0 status bits of vip_0 channel_7 125 s 3.072 mhz s_0c1 s_0c2 s_0c3 s_0c4 s_0c5 c_0c6 c_0c0 c_0c7 c_0 command bits to vip_0 commands bits to vip_0 channel_7 c_0c1 c_0c2 c_0c3 c_0c4 c_0c5 0 1 2 31 0 1 2 31 0 1 2 31 c_0 ... s_0 ... 3x32-bit empty 3x32-bit empty note: c_0 refers to cmd_0, s_0 to stat_0 c_0c0 refers to cmd_0_0, s_0c0 to stat_0_0 fsc cmd / 125 s vip_0 vip_1 stat vip_0 ch0 ch7 vip_2 vip_1 ch0 ch7 vip_2 ch0 ch7 3 empty 32-bit words 3 empty 32-bit words 3 empty 32-bit words vip_0 ... reserved
delic interface description preliminary data sheet 3-7 2003-08 commands to vip_n (cmd_n, n = 0 ... 2) initialization and control information for each vip is sent by delic in the following sequence every 125 s via the iom-2000 cmd line (32 cmd_n bits per vip_n): note: all bits are programmed in vip command register (vipcmr0..2). commands to vip_n, channel_m (cmd_n_m, m = 0 ... 7) initialization and control information for each vip channel is sent by delic in the following sequence every 125 s via the iom-2000 cmd line (32 cmd_n_m bits per vip_n channel_m): note: all bits except wr_st, smini(2:0) and msync are programmed in transiu initialization channel command register (ticcr); bits wr_st, smini(2:0) and msync reside in the transiu tx data ram. 31 24 xxx x x x x x 23 16 xxx x x x x x 15 8 xxx x rd_n pllpps sh_fsc delre 70 cmd_n delch(2:0) exref refsel(2:0) wr_n 31 24 cmd_n_m fil smini(2:0) msync exlp plls pd 23 16 x dhen x x pdown loop tx_en pllint 15 8 aac(1:0) bbc(1:0) owin(2:0) mf_en 70 mode(2:0) mosel(1:0) wr_st rd wr
delic interface description preliminary data sheet 3-8 2003-08 status from vip_n (n = 0 ... 2) status information is sent by each vip in the following sequence via the stat line (32 stat_n bits per vip_n): note: bits delay are read from vip status register (vipstr) in transiu. x = unused status from vip_n, channel_m (m = 0 ... 7) status information is sent by each vip channel in the following sequence via the stat line (32 stat_n_m bits per vip_n channel_m): note: marked bits (*) are not evaluated by the delic, only for vip testing. bits slip, fecv and are directly accessible in the transiu receive data ram. x = unused 31 24 stat_n xxxxxxxx 23 16 xxxxxxxx 15 8 xxxxxxxx 70 delay(7:0) 31 24 stat_n_m xxxxxxxx 23 16 xxxxxxxx 15 8 xxxxxxxx 70 x msync* fcv* fsync* slip fecv rxsta(1:0)
delic interface description preliminary data sheet 3-9 2003-08 3.2.3 u pn state machine 3.2.3.1 info structure on the u pn interface signals controlling and indicating the internal state of all u pn transceiver state machines are called infos. four different infos (info 0, 1w, 1, 2, 3, 4) may be sent over the u pn interface, depending on the actual state (synchronized, activated, pending activation, ...). when the line is deactivated, info 0 (=no signal on the line) is exchanged by the u pn transceivers at either end of the line. when the line is activated, info 3 (in upstream direction) and info 4 (in downstream direction) are continuously sent. info 3 and 4 contain the transmitted data (b1, b2, d, m). info 1/2 are used for activation and synchronization. note: 1) the m channel superframe contains: cv code violation [1 kbit/s (once in every fourth frame)] s bits transparent [1 kbit/s channel] t bits transparent [2 kbit/s channel] 2) dc balancing bit; f = framing bit table 3-3 info structure on u pn interface name direction description info 0 upstream downstream no signal on the line info 1w upstream asynchronous wake signal 4 khz burst rate f0001000100010001000101010100010111111 code violation in the framing bit info 1 upstream 4 khz burst rate f000100010001000100010101010001011111m 1) dc code violation in the framing bit info 2 downstream 4 khz burst rate f000100010001000100010101010001011111m 1) code violation in the frame bit info 3 upstream 4 khz burst rate no code violation in the framing bit user data in b, d and m channels b channels scrambled, dc bit 2) optional info 4 downstream 4 khz burst rate no code violation in the framing bit user data in b, d and m channels b channels scrambled, dc bit 2 ) optional
delic interface description preliminary data sheet 3-10 2003-08 3.2.3.2 u pn mode state diagram figure 3-6 u pn state diagram i3 state ind. cmd. ix iy out p interface upn interface delphi up sm.vsd in reset tim res i0 * pend. deact. tim dr i0 i0 g4 wait for dr di dr i0 i0 deactivated di dc i0 i0 pend. act. ar dc arx i2 i1w synchronized uai dc arx, ai i4 i1 activated ai i4 i3 resynchron. rsy dc arx i2 i1 dr dr dr dr res i1w test mode tim tm1 tm2 it1 it2 * tm1 tm2 reset dr dc arx i1 i3 dc arx, ai dr i1, i3 i1 dc dr i0 note : tm2 = send continuous pulses tm1 = send single pulses it1 = test signal invoked by tm1 it2 = test signal invoked by tm2 arx = ar, ar2 uncond. transitions by: res, tm1, tm2, dr
delic interface description preliminary data sheet 3-11 2003-08 the u pn state machine has unconditional and conditional states (refer to figure 3-6 ): unconditional states reset this state is entered unconditionally after a low appears on the reset pin or after the receipt of command res (software reset). the analog transceiver part is disabled (transmission of info 0) and the u pn interface awake detector is inactive. hence, activation from terminal (te) is not possible. test mode the test signal (it i ) sent to the u pn interface in this state is dependant on the command which originally invoked the state. tm1 causes single alternating pulses to be transmitted (it 1 ); tm2 causes continuous alternating pulses to be transmitted (it 2 ). the burst mode technique normally employed on the u pn interface is suspended in this state and the test signals are transmitted continuously. pending deactivation to access any of the conditional states from any of the above unconditional states, the pending deactivation state must be entered. this occurs after the receipt of a dr command. in this state the awake detector is activated and the state is left only when the line has settled (i.e., info 0 has been detected for 2 ms) or by the command dc. note: although dr is shown as a normal command, it may be seen as an unconditional command. no matter which state the lt is in, the reception of a dr command will always result in the pending deactivation state being entered. conditional states wait for dr this state is entered from the pending deactivation state once info 0 or dc has been identified. from here the line may be either activated, deactivated or a test loop may be entered. deactivated this is the power down state of the physical protocol. the awake detection is active and the device will respond to an info 1w (wake signal) by initiating activation.
delic interface description preliminary data sheet 3-12 2003-08 pending activation this state results from a request for activation of the line, either from the terminal (info 1w) or from the layer-2 device (ar, ar2). info 2 is then transmitted and the dsp waits for the responding info 1 from the remote device. synchronized this state is reached after synchronization upon the receipt of info 1, i.e. after a maximum of 10 ms. in this state, info 2 is supplied to the remote terminal for synchronization. activated info 1 has a code violation in the framing bit (f-bit), whereas info 3 has none. upon the reception of two frames without a code violation in the f bit, the activated state is entered and info 4 is transmitted. the line is now activated; info 4 is sent to the remote and info 3 is received from the remote. re synchronization if the recognition of info 3 fails, the receiver will attempt to resynchronize. upon entering this state, info 2 is transmitted. this is similar to the original synchronization procedure in the pending activation state (the indication given to layer 2 is different). however, as before, recognition of info 1 leads to the synchronized state. table 3-4 u pn state machine codes command abbr. code remark deactivate request dr 0000 initiates a complete deactivation from the exchange side by transmitting info 0 (x) reset res 0001 (x) test mode 1 tm1 0010 transmission of pseudo-ternary pulses at 2 khz frequency (x) test mode 2 tm2 0011 transmission of pseudo-ternary pulses at 192 khz frequency (x) activate request ar 1000 used to start an exchange initiated activation activate request test loop 2 ar2 1010 transmission of info 2, switching of loop 2 (at te), t bit set to one
delic interface description preliminary data sheet 3-13 2003-08 (x) unconditional commands note: the u pn state machine does not support loops. so neither c/i commands nor indications are provided by the mailbox protocol. an loop can be programmed by setting bits ticcmr:loop and ticcmr:exlp for the respective channel. activate indication = "blocked" ai 1100 transmission of info 4, t bit set to zero deactivate confirmation dc 1111 deactivation acknowledgement, quiescent state indication abbr. code remark timing tim 0000 deactivate state, activation from the line not possible resynchronizing rsy 0100 receiver is not synchronous activate request ar 1000 info 1w received u only activation indication uai 0111 info 1 received, synchronous receiver activate indication ai 1100 receiver synchronous, i.e., activation completed deactivate indication di 1111 info 0 or dc received after deactivation request table 3-4 u pn state machine codes (continued) command abbr. code remark
delic interface description preliminary data sheet 3-14 2003-08 3.2.4 s/t state machine a finite state machine in the delic controls the vip s/t line activation/deactivation procedures and transmission of special pulse patterns. such actions can be initiated by primitives (infos) on the s/t interface or by c/i codes sent via the mailbox. depending on the application mode and the transfer direction, the s/t state machines support different codes in conditional and unconditional states: lt-s mode codes: data downstream = commands: reset, test mode, activate req, .. data upstream = indications: not sync, code violation, timer out, .. states: deactivated, activated, pending, lost framing, test mode the state diagram is shown in figure 3-7. lt-t mode codes data upstream = commands: reset, test, activate request,.. data downstream = indications: command x acknowledged,.. conditional states: power up, pending deactivation, synchronized, slip detected,.. the state diagram is shown in figure 3-8. unconditional states may be entered from any conditional state and should be left with the command tim: test mode, reset state,.. the s/t layer-1 activation and deactivation procedures implemented in the delic are similar to the ones implemented in the peb 2084, quat-s. 3.2.4.1 lt-s mode table 3-5 lt-s state machine codes command abbr. code remark deactivate request dr 0000 initiates a complete deactivation from the exchange side by transmitting info 0 (x) reset res 0001 (x) test mode 1 tm1 0010 transmission of pseudo-ternary pulses at 2 khz frequency (x) test mode 2 tm2 0011 transmission of pseudo-ternary pulses at 96 khz frequency (x)
delic interface description preliminary data sheet 3-15 2003-08 (x) unconditional commands note: the lt-s state machine does not support loops. so neither c/i commands nor indications are provided by the mailbox protocol. a loop can be programmed by setting bits ticcmr:loop and ticcmr:exlp for the respective channel. activate request ar 1000 used to start an exchange initiated activation deactivate confirmation dc 1111 deactivation acknowledgement, quiescent state indication abbr. code remark timing tim 0000 resynchronizing rsy 0100 receiver is not synchronous activate request ar 1000 info 0 received code violation received cvr 1011 after each multi-frame the reception of at least one illegal code violation is indicated four times activate indication ai 1100 receiver synchronous, i.e., activation completed deactivate indication di 1111 timer (32 ms) expired or info 0 received after deactivation request table 3-5 lt-s state machine codes (continued) command abbr. code remark
delic interface description preliminary data sheet 3-16 2003-08 figure 3-7 state diagram of lt-s mode state ind. cmd. ix iy out s interface delphi lt-s sm.vsd in reset tim res i0 * test mode tim scp ssp it1 it2 * g4 pend. deact. tim dr i0 i0 g4 wait for dr di dr i0 * g1 deactivated di dc i0 i0 g2 pend. act. ar dc ar i2 i3 g3 activated e=d ar dc ar i4 i3 g2 lost framing rsy dc ar i2 i3 res any state dc dr dc dr dr dr dr dr scp ssp ard 1) ard 1) ard 1) i3 i0 dc i0 or 32ms i3 p interface reset note : tm2 = send continuous pulses tm1 = send single pulses it1 = test signal invoked by tm1 it2 = test signal invoked by tm2 any state i3
delic interface description preliminary data sheet 3-17 2003-08 lt-s mode states g1 deactivated the line interface is not transmitting. there is no signal detected on the s interface, and no activation command is received. g2 pending activation as a result of an info 1 detected on the s line or an ar command, the line interface begins transmitting info 2 and waits for reception of info 3. the timer to supervise reception of info 3 is to be implemented in software. in case of an arl command, loop 2 is closed. g3 activated normal state where info 4 is transmitted to the s interface. the line interface remains in this state as long as neither a deactivation nor a test mode is requested, and the receiver does not loose synchronism. when receiver synchronism is lost, info 2 is sent automatically. after reception of info 3, the transmitter continues sending info 4. g2 lost framing this state is reached when the line interface has lost synchronism in the state g3 activated. g4 pending deactivation this state is triggered by a deactivation request dr. it is an unstable state: status di (state ?g4 wait for dr?) is issued by the delic when either info 0 is received, or an internal timer of 32 ms expires. g4 wait for dr final state after a deactivation request. the line interface remains in this state until a response to di (in other words dc) is issued. test mode 1 single alternating pulses are sent on the s interface (2 khz repetition rate). test mode 2 continuous alternating pulses are sent on the s interface (96 khz).
delic interface description preliminary data sheet 3-18 2003-08 3.2.4.2 lt-t mode (x) unconditional commands note: the lt-t state machine does not support loops. so neither c/i commands nor indications are provided by the mailbox protocol. a loop can be programmed by setting bits ticcmr:loop and ticcmr:exlp for the respective channel. table 3-6 lt-t mode state machine codes (conditional states) command abbr. code remark timing request tim 0000 requests the line interface to change into power-up state reset res 0001 reset of state machine. transmission of info 0. no reaction to incoming infos (x) test mode 1 tm1 0010 transmission of single pulses on the s/t- interface. the pulses are transmitted with alternating polarity at a frequency of 2khz. (x) test mode 2 tm2 0011 transmission of continuous pulses on the s/t-interface. the pulses are sent with alternating polarity at a rate of 96 khz. tm2 is an unconditional command (x). activate request, priority 8 ar8 1000 activation request with priority 8 for d- channel transmission. this command is used to start a lt-t initiated activation. d-channel priority 8 is the highest priority. it should be used to request signaling information transfer. activate request, priority 10 ar10 1001 activation request with priority 10 for d- channel transmission. this command is used to start a lt-t initiated activation. d-channel priority 10 is a lower priority. it should be used to request packet data transfer. deactivate indication di 1111 this command forces the line interface into ?f3 power down? mode.
delic interface description preliminary data sheet 3-19 2003-08 indication abbr. code remark deactivate request dr 0000 deactivation request if left from f7/f8 reset res 0001 reset acknowledge test mode 1 tm1 0010 tm1 acknowledge test mode 2 tm2 0011 tm2 acknowledge slip detected slip 0011 frame wander larger than +/- 25 s resynchronization during level detect rsy 0100 signal received, receiver not synchronous power up pu 0111 line interface is powered up activate request ar 1000 info 2 received code violation received cvr 1011 after each multiframe the reception of at least one illegal code violation is indicated four times. activate indication with priority class 8 ai8 1100 info 4 received, d-channel priority is 8 or 9 activate indication with priority class 10 ai10 1101 info 4 received, d-channel priority is 10 or 11 deactivate confirmation dc 1111 line interface is powered down
delic interface description preliminary data sheet 3-20 2003-08 figure 3-8 lt-t mode state diagram (conditional and unconditional states) x 1) dr for transition from f7 or f8 2) ar stands for ar8 or ar10 3) ai stands for ai8 or ai10 4) tmi stands for tm1 or tm2 5) it1 = test signal invoked by it1 it2 = test signal invoked by it2 to1: 16 ms to2: 0.5 ms f3 pending deact. dr 1) i0 i0 f3 power down dc di i0 i0 ar i2 tim f3 power up pu tim i0 i0 di tim di i2 di*to2 (from f6) di (from f7, f8) tim*to2 (from f6) tim (from f7, f8) i0 f8 lost framing rsy i0 x i4 i0*to1 i0*to1 ar di i2 f7 activated ai 3) ar 2) i3 i4 f6 synchronized ar i3 i2 x f5 unsynchronized rsy i0 ix i2 i0 f4 pending act. pu ar 2) i1 i0 x i4 i2 i2 i4 ix ix tim i4 i4 i4 tim di tim test mode i tmi 4) tmi 4) it 5) * di reset res res i0 * di tim res res delphi reset pin any state tmi 4)
delic interface description preliminary data sheet 3-21 2003-08 lt-t mode (conditional states) f3 power down this is the deactivated state of the physical protocol. the receive line awake unit is active. f3 power up this state is similar to ?f3 power down?. the state is invoked by a command tim = ?0000? (or di static low). f3 pending deactivation the line interface reaches this state after receiving info 0 (from states f5 to f8). from this state an activation is only possible from the line (transition ?f3 pending deactivation? to ?f5 unsynchronized?). the power down state may be reached only after receiving di. f4 pending activation activation has been requested from the terminal; info 1 is transmitted; info 0 is still received; ?power up? is transmitted in the c/i channel. this state is stable: timer t3 (itu i.430) is to be implemented in software. f5/8 unsynchronized at the reception of any signal the vip ceases to transmit info 1, adapts its receiver circuit, and awaits identification of info 2 or info 4. this state is also reached after the line interface has lost synchronism in the states f6 or f7 respectively. f6 synchronized when the vip receives an activation signal (info 2), it responds with info 3 and waits for normal frames (info 4). f7 activated this is the normal active state with the layer 1 protocol activated in both directions. from state ?f6 synchronized?, state f7 is reached almost 0.5 ms after reception of info 4. f7 slip detected when a slip is detected between the t interface clocking system and the iom-2 interface clocks (phase wander of more than 25 s, data may be disturbed) the line interface enters this state, synchronizing again the internal buffer. after 0.5 ms this state is relinguished.
delic interface description preliminary data sheet 3-22 2003-08 lt-t mode (unconditional states) the unconditional states should be left with the command tim. test mode 1 single alternating pulses are sent on the t interface (2 khz repetition rate). test mode 2 continuous alternating pulses are sent on the t interface (120 khz). reset state a hardware or software reset (res) forces the line interface to an idle state where the analog components are disabled (transmission of info 0) and the t line awake detector is inactive.
delic interface description preliminary data sheet 3-23 2003-08 3.3 iom ? -2 interface iom-2 is a standardized interface for interchip communication in isdn line cards for digital exchange systems developed by alcatel, siemens, plessey and italtel. the iom-2 interface is a four-wire interface with a bit clock, a frame clock and one data line per direction. it has a flexible data clock. this way, data transmission requirements are optimized for different applications. figure 3-9 iom ? -2 interface in digital linecard mode note: in linecard mode, 8 identical iom-2 subchannels are provided. in analog linecards, a 6-bit c/i channel is available for signaling information. in digital linecards, a dedicated 2-bit d-channel carries the signaling information. 3.3.1 signals / channels fsc frame synchronization clock, 8 khz dcl data clock, up to 4.096 mhz *) dd data downstream, up to 4.096 mbit/s *) du data upstream, up to 4.096 mbit/s *) b1, b2 user data channels, 64 kbit/s each monitor monitor channel d signaling channel, 16 kbit/s c/i command/indication channel mr monitor receive handshake signal mx monitor transmit handshake signal *) for detailed clock and data rates, refer to iomu feature description in chapter 4.3.2
delic interface description preliminary data sheet 3-24 2003-08 3.4 p interface the p interface may be operated in different modes. this chapter describes how to configure the delic to each mode. 3.4.1 intel/siemens or motorola mode the processor mode is selected by the mode input pin of the delic. "low" level selects siemens/ intel mode, "high" level selects motorola mode. 3.4.2 de-multiplexed or multiplexed mode in both modes, the a-bus and the d-bus are used in parallel. the a-bus should be connected to the 8 lsbs of ad-bus, coming from the p, also in multiplexed mode. the mode is determined according to the ale input pin. when ale is permanently driven to ?1?, the delic works in de-multiplexed mode. otherwise the delic works in multiplexed mode. the next figure describes the connection of the delic to the address and data buses in the different modes. note: motorola mode is used only with de-multiplexed ad bus. intel/infineon mode may be used with both, multiplexed or de-multiplexed ad bus.
delic interface description preliminary data sheet 3-25 2003-08 figure 3-10 delic in multiplexed and in de-multiplexed bus mode note: in both modes only the 7 lsbs of a-bus or ad/bus are connected to the address inputs of the delic. in dma mode dack /a4 input pin is used as dack , and a4 is internally driven to ?0?. in this case a4 of the p a/ad-bus is also not connected to the delic. 3.4.3 dma or non-dma mode the internal interface between the on-chip dsp and p is established by two mailboxes: a ?general? mailbox and a dedicated dma mailbox. the non-dma mode provides the option to combine them together building a double-sized ?general? mailbox. the delic is configured to dma or non-dma mode by a dedicated bit in the p interface configuration register (mcfg:dma). dma mode the dma mailbox can be accessed only by a dma controller. the dack input pin (together with the rd and wr signals) is used to access the dma mailbox. only the general mailbox can be accessed directly by the p. in dma mode, the pin dack /a4 is multiplexed mode p delic ad d a ale ale latch de-multiplexed mode p delic d d a ale latch ?1? a 8 7 8 7
delic interface description preliminary data sheet 3-26 2003-08 used as dack , and a4 of the a-bus or ad-bus coming from the p must not be used as an address line for the delic. in this case a4 is driven internally to ?0?. note: in de-multiplexed mode ad4 should be connected to delic?s d4input pin. non-dma mode this is the default mode (after reset).the general mailbox and the dma mailbox data registers are concatenated into one double-sized general mailbox, accessible by the p. this broad mailbox consists of a dedicated p mailbox and a dsp mailbox. each of them contains 32 data bytes and 1 command byte. in non-dma mode, dack /a4 is used as a4, in order to include the dma mailbox data registers in the p interface address space. 3.4.4 delic external interrupts the delic contains only one source for an external interrupt - the general mailbox. this interrupt source is the ocmd register of the dsp mailbox. releasing the interrupt is done by the p resetting bit obusy:busy. masking it may be done by resetting the mask bit of the p interface configuration register (mcfg:imask). the interrupt vector issued is the contents of the dsp mailbox command register mcmd. in motorola mode, the interrupt vector is issued upon the first iack pulse, while in siemens/intel mode it is issued upon the second iack pulse. in the latter case, the interrupt vector due to the first iack pulse (if needed), should be issued by an external interrupt controller.
delic interface description preliminary data sheet 3-27 2003-08 3.5 jtag test interface the delic provides fully ieee standard 1149.1 compatible boundary scan support to allow cost effective board testing. it consists of: complete boundary scan test test access port controller (tap) five dedicated pins: jtck, tms, tdi, tdo (according to jtag) and an additional trst pin to enable asynchronous resets to the tap controller one 32-bit idcode register 3.5.1 boundary scan test depending on the pin functionality one or two boundary scan cells are provided. when the tap controller is in the appropriate mode data is shifted into/out of the boundary scan via the pins tdi/tdo using a clock of up to 6.25 mhz on pin jtck. the sequence of the delic pins can be taken from the bsdl files. 3.5.2 tap controller the test access port (tap) controller implements the state machine defined in the jtag standard ieee 1149.1. transitions on the pin tms cause the tap controller to perform a state change. the tap controller supports a set of 5 standard instructions: extest is used to verify the board interconnections. when the tap controller is in the state ?update dr?, all output pins are updated with the falling edge of jtck. when it has entered state ?capture dr? the levels of all input pins pin type number of boundary scan cells usage input 1 input output 2 output, enable table 3-7 tap controller instruction codes code instruction function 0000 extest external testing 0001 intest internal testing 0010 sample/preload snap-shot testing 0011 idcode reading id code register 1111 bypass bypass operation
delic interface description preliminary data sheet 3-28 2003-08 are latched with the rising edge of jtck. the in/out shifting of the scan vectors is typically done using the instruction sample/preload. intest supports internal chip testing. when the tap controller is in the state ?update dr?, all inputs are updated internally with the falling edge of jtck. when it has entered state ?capture dr? the levels of all outputs are latched with the rising edge of jtck. the in/out shifting of the scan vectors is typically done using the instruction sample/preload. note: 0011 (idcode) is the default value of the instruction register. sample/preload provides a snap-shot of the pin level during normal operation or is used to either preload (tdi) or shift out (tdo) the boundary scan test vector. both activities are transparent to the system functionality. idcode the 32-bit identification register is serially read out via tdo. it contains the version number (4 bits), the device code (16 bits) and the manufacturer code (11 bits). the lsb is fixed to ?1?. the code for the delic version 1.1 is ?0001?. note: in the state ?test logic reset? the code ?0011? is loaded into the instruction code register. bypass , a bit entering tdi is shifted to tdo after one jtck clock cycle, e.g. to skip testing of selected ics on a printed circuit board. version device code manufacturer code output 0001 0000 0000 0101 0111 0000 1000 001 1 --> tdo
delic peb 20571 functional description preliminary data sheet 4-1 2003-08 4 functional description as the functionality of the delic-pb comprises the functionality of the delic-lc, the following chapter discribes the functionality of the delic-pb. the differences between the two chip versions can be seen below: note: as the functionality is also dependent on the firmware package, please also refer to the respective documentation. table 4-1 differences between delic-lc - delic-pb functionality delic-lc delic-pb ghdlc channels (maximum configuration) cha. 0 cha. 0..3 hdlc channels (maximum configuration) cha. 0..23 cha. 0..31 dma interface not available available dma- mailbox not available; it is used to increment the general mailbox can be used for dma operation or as general mailbox pinout free programmability of dsp-system no yes
delic peb 20571 functional description preliminary data sheet 4-2 2003-08 4.1 functional overview and block diagram figure 4-1 block diagram upn delic jtag pll 5 p mail box 16 8 16 ... 2 vip/ vip-8 p siemens c166 6 8 x u pn / s/t 0 1 s/t 4 dmac memory 3.3 v 2 x 2.048 mbit/s or 1 x 4.096 mbit/s 3 vip 2 3 subscribers 5 dma mail box interrupt controller different lines: upn or s/t pcm unit ghdlc unit hdlc unit transiu vip 1 vip 0 dsp oak + memory different lines t/r s/t upn uk0 pri layer-1 ics 2x iom /gci iom-2000/ lnc1 refclk 16.384 mhz clocks dsp 61.44 mhz p bus dma interface test int pcm/ lnc2..3 lnc0 3.3 v 5v iom unit mux mux
delic peb 20571 functional description preliminary data sheet 4-3 2003-08 4.2 iom-2000 transceiver unit 4.2.1 transiu overview of features the transiu controls up to 24 layer-1 channels via up to three vip/ vip8 connected on iom-2000 interface iom-2000 interface: all channels may be programmed in the transiu to: ? u pn interface ? s/t interface in lt-s (subscriber master) or lt-t (trunk slave) mode note: the number of s/t interfaces in vip peb 20590 is limited to 4. therefore it is required to program the transiu correctly to the required mode (refer to transiu register description) data rates: 3.072 mbit/s (1 vip), 6.144 mbit/s (2 vips) or 9.216 mbit/s (3 vips) data and maintenance bit handling for s/t and u pn interface, including multiframe control and d-channel collision control. 4.2.2 transiu initialization reset status all iom-2000 channels are configured to s/t interface, lt-s mode the data rate in the transiu is set to 3.072 mbit/s all buffers related to the iom-2000 are undefined the command and status buffers have the value ?0? channel programming every iom-2000 channel may be configured in the transiu as: u pn mode s/t channel in lt-s mode s/t channel in lt-t mode data rate programming the transiu supports three configurations regarding the number of vips connected via iom-2000: one vip connected at data rate of 3.072 mbit/s: 8 iom-2000 channels at a clock rate of 3.072 mhz two vips connected at data rate of 6.144 mbit/s: 16 iom-2000 channels at a clock rate of 6.144 mhz three vips connected at data rate of 9.216 mbit/s: 24 iom-2000 channels at a clock rate of 12.288 mhz. (note the difference between clock rate and actual data rate)
delic peb 20571 functional description preliminary data sheet 4-4 2003-08 4.2.3 initialization of vip during startup the vip requires 3 frames with the right fsc and dcl_2000 to synchronize to the delic. during this time the vip is not able to detect commands or data from the delic. 4.2.4 s/t mode control and framing bits on iom-2000 4.2.4.1 framing bit (f-bit) the framing (f) bit is recognized on the iom-2000 interface, when both data and control bits are equal to ?1?. in the transmit direction the data and control bits are inserted by the transiu at the beginning of every transmitted frame; in the receive direction the framing bit is used for frame start recognition. 4.2.4.2 multiframing bits in s/t interface, the multiframe includes 20 s/t frames. the start of a multiframe is indicated by the m- and f a -bits (the m-bit is set to ?1? in every 20-th frame, the f a -bit is set to ?1? in every 5-th frame). the s/q channel provides the additional capability for data exchange between lt-s and te or between the central office (co) and the lt-t at the multiframe level. in the lt-s- to-te direction the s-channel (s-bit in s/t frame) is used. in the opposite direction (te to lt-s) the data is transferred on the q-channel. the q-bits are defined to be the bits in the f a bit position of every 5-th frame. the q-bit position is identified by f a = ?1? in the te to lt-s direction. a multiframe is provided for structuring the q-bits in groups of four (q1-q4). the q- and s-channel coding with respect to the frame number is shown in table 4-2 . figure 4-2 s/q channel assignment vip te co lt-s lt-t s s q q delic iom-2000
delic peb 20571 functional description preliminary data sheet 4-5 2003-08 note: 1.only frame positions (within the 20-frame multiframe) that carry s- or q-channel information are shown here 2.the q- and s-bits, which are not used, are set to ?1?. on the iom-2000 interface, the s/t multiframe information is included in the dx/dr data stream (transparently to the vip). the values of the multiframe are controlled by the dsp software in the delic. when multiframe synchronization is not achieved or lost, the vip mirrors the received f a bits. once the multiframe synchronization is established, the dsp sends the multiframe synchronization command to the vip (msync bit). upon reception of the msync, the vip stops mirroring the f a -bit. 4.2.4.3 f a /n bit in the transmit direction the f a /n bit pair is coded in such a way that n is the binary opposite of the f a . the f a bit is equal to binary ?0?, except every 5-th frame when it is set to ?1?, which indicates the q-bit position to the te. the receive direction, the f a bit positions represent the q-channel. 4.2.4.4 dc-balancing bit (l-bit) in transmit (downstream) direction the l-bi t is generated in compliance with itu-t i.430: a balance bit is ?0? if the number of 0?s following the previous balance bit is odd. a balance bit is ?1? if the number of 0?s following the previous balance bit is even. table 4-2 s/t mode multiframe bit positions frame number lt-s to te or co to lt-t, f a bit position lt-s to te or co to lt-t, m-bit lt-s to te or co to lt-t, s-bit te to lt-s or lt-t to co f a bit position 1 11s11q1 2 00s210 6 10s12q2 7 00s220 11 1 0 s13 q3 12 0 0 s23 0 16 1 0 s14 q4 17 0 0 s24 0 ... ... ... ... ...
delic peb 20571 functional description preliminary data sheet 4-6 2003-08 it is inserted by the vip according to the balancing bit control (bbc) bit sent to the vip by the delic via the cmd line. in receive (upstream) direction, the dc balancing bit is received on the line, but not evaluated 4.2.5 u pn mode control and framing bits on iom-2000 4.2.5.1 framing bit (lf-bit) on the u pn interface the framing (lf) bit is always logical ?1?. in the transmit direction the lf-bit is inserted by the transiu at the beginning of every transmitted u pn frame. the vip assumes the start of the u pn frame when detecting the first '1' (lf-bit) in the data stream on iom-2000 dx line together with the 8 khz iom-2000 fsc pulse. this is required due to the 8 khz clock rate of the fsc signal in comparison to the 4 khz frame length in the u pn interface. the code violation in the lf position is generated by the vip when info1 is transmitted, according to the dsp command bits smini(2:0). in the receive direction the first ?1? recognized on the line after ?no signal?, which is represented by logic ?0?, is treated as the lf-bit. the code violation in the lf-bit position is recognized by the vip when info 2 is received. this information is forwarded to the delic as part of the vip receiver status bits rxsta(1:0). 4.2.5.2 multiframing bit (m-bit) on the u pn interface, multiframes are composed of four u pn frames. the multiframe is included at the m-bit position. every fourth m-bit, a code violation indicates the start of a new multiframe. in transmit direction, the vip extracts the multiframe bits out of the iom-2000 data coming from delic and inserts them in the u pn frame at the line side. in receive direction, the vip extracts the multiframe bits out of the data coming from the u pn line and inserts them in the iom-2000 frame to the delic. a multiframe counter in the vip guarantees the timing of the multiframe. it is synchronized (reset) every 20th u pn frame (=every 40th iom-2000 frame) by the command bit ?sh_fsc? issued by the delic. note: the sh_fsc bit performs the functionality of the short fsc pulse in octat-p and quat-s. t-bit the t-bit received on the u pn line is inserted by the vip in the iom-2000 data receive (dr) line at the multiframe (m-bit) position in every frame; i.e. not only at the usual t-bit position every third frame, but also at the s-bit position and the code violation (cv)
delic peb 20571 functional description preliminary data sheet 4-7 2003-08 position. the delic dsp software may evaluate the received t-bit to provide the user with an additional data channel (under consideration). note that this is an additional feature to the octat-p. in transmit direction, the t-bit value is sent in the data stream from the delic to the vip, and passed on transparently to the u pn terminal. the t-bit value may be programmed in delic?s data ram. it is required e.g. for dect synchronization. s-bit the s-bit received on the u pn line interface is extracted by the vip out of the data stream, and is logical or? ed with the detected far-end code violation. the result is sent to the delic as status bit ?fecv?. in transmit direction, the s-bit value is sent in the data stream from the delic to the vip, and passed on transparently to the u pn terminal. the s-bit value may be programmed in delic?s data ram. it is required e.g. for switching a digital loop in the terminal. cv-bit the code violation bit received on the line is not transmitted to the delic. 4.2.5.3 dc-balancing bit a dc-balancing bit is inserted by the vip according to the balancing bit control (bbc) bit transmitted to the vip on the command line. in receive direction, the dc balancing bit is received, but not evaluated. 4.2.6 iom-2000 command and status interface all command/status bits used for vip channel programming are divided into one group used only during initialization, and one group used during normal operation. initialization mode command bits the bits of this group are used for vip initialization or in operation modes where an immediate reaction is not required. the initialization group includes command bits and the channel address, stored in register ticcmr . note that the usage of this group of bits is limited in a way that only one channel may be accessed in each frame. in test mode, the command word to vip_n (cmd_n) and to channel_m of vip_n (cmd_n_m) may be read by the delic in the next frame after issuing bits ?rd_n? or ?rd?. the vip mirrors the command word exactly as it was received, despite the bits ?wr?, ?wr_st?, ?rd?. the vip status is saved in the transiu initialization status (ticstr) register, which includes status bits and the channel address. note: the commands must not be read during normal operation, since in this case the reporting of the vip status to the delic would not be possible.
delic peb 20571 functional description preliminary data sheet 4-8 2003-08 operational mode command/status bits the bits of this group are used during normal operation, hence they are evaluated in every frame. they include all vip receiver status bits and some of the command bits. the operational mode command/status bits are buffered in the data ram. the vip receiver status bits do not reflect a status change, but the status itself, i.e. the current value of the line interface infos, until the values change. the fecv is only reported to the delic upon changes. command/status transmission the command/status bits are transmitted/received by the transiu at the same rate as data transmission rate, starting with the 8 khz fsc. transmit direction the command information per vip is prepared by the dsp in the vipcmr0-2 registers the command bits from initialization command group are prepared by the dsp in the iccmr register for one of the channels transiu operation mode command format in the data ram: 765 4 3 2 1 0 data byte 1 data byte 2 data byte 3 xxx smini(2:0) msync wr_st wr_st write command to tst1 bits (s/t, u pn ) 0 = data sent in these bits is invalid 1 = smini(2:0) and msync contain valid data
delic peb 20571 functional description preliminary data sheet 4-9 2003-08 receive direction the received status per vip is stored in the vipstr0-2 registers if the ?read_status? command was transmitted in the previous frame for one of the channels, the received status from this channel is saved in the ticstr register together with the 5-bit channel address transiu operation mode status format in the data ram: msync multiframe synchronization (lt-t) 0 = vip mirrors the f a -bit 1 = vip stops the f a -bit mirroring (for multiframe synchronization) smini(2:0) state machine initialization (s/t, u pn ) command to vip from the delic layer-1 state machine. depending on the state, the vip may transmit data on the u pn or s/t interface. the vip responds by sending the receiver status bits stat_n_m.rxsta(1:0) to the delic. 000 = info 0 in s/t or u pn 001 = info 1w in u pn 010 = info 1 in lt-t, info 2 in lt-s or u pn 011 = info 3 in lt-t, info 4 in lt-s or u pn 100 = test mode ?send continuous pulses scp?: ?1s? transmitted at 96 khz (u pn ) and at 192 khz s/t) 101 = test mode ?send single pulses ssp? (at 2 khz burst rate) note: all other states are reserved 76543210 data byte 1 data byte 2 data byte 3 x msync fcv fsync slip fecv rxsta(1:0)
delic functional description preliminary data sheet 4-10 2003-08 note: with * marked bits are not evaluated by the delic, only for vip testing. bits slip, fecv and are directly available to the dsp software in the transiu receive data ram. rxsta(1:0) receiver status change (s/t, u pn ) 00 = receiver is not synchronized to the line; no signal on line (info 0) 01 = level detected on line (any signal) (inf 1 in lt-s mode) 10 = receiver is synchronized to the line, but not activated (info 2 in lt-t mode) 11 = receiver is synchronized and activated (info 4 for lt-t mode info 3 for lt-s and u pn ) fecv far-end code violation (s/t, u pn ) 0 = normal operation 1 = illegal code: fecv according to ansi t1.605 detected (s/t) slip frame slip detected (lt-t) 0 = no frame slip detected 1 = a frame slip of more than 25 s (tbd) was detected on the lt-t channel fsync * f-bit synchronous (s/t + u pn test mode only!!) fcv * code violation in f-bit detected (u pn test mode only!!) msync / ld * multiframe synchronous (u pn ), level detected (s/t), test mode!!
delic peb 20571 functional description preliminary data sheet 4-11 2003-08 4.2.7 iom-2000 data interface data processing and frame handling in the transiu is fully dsp controlled. serial data received and transmitted on the iom-2000 interface is arranged in the shift receive ram and shift transmit ram. the dsp processed bytes are stored in the transiu current buffer. every 8 khz frame the transiu and dsp current buffers are switched. 4.2.7.1 u pn mode the data is received and transmitted at a nominal bit rate of 384 kbit/s. in the first half of the 4 khz u pn frame data is transmitted and ?zeros? are received, in the second half of the frame ?zeros? are transmitted and data is received. scrambling and de-scrambling of the b-channel data is done automatically. the received and transmitted data is stored in the data ram in the following format: u pn mode receive / transmit data format in transmit direction, depending on the multiframe position, the m-bit contains either the t-bit or the s-bit with the following functionality: t-bit: a) d-channel available info to the terminal b) dect synchronization signal s-bit: switches remote loop in terminal device 4.2.7.2 u pn scrambler/descrambler b-channel data on all u pn channels of the iom-2000 interface is scrambled to give a flat continuous power density spectrum on the line. scrambling is done according to itu-t v.27 with the generator polynomial 1 + x 6 + x 7 initialization via history ram (hram) the scrambler is activated/de-activated for each u pn channel separately by a dsp write to the history ram address. 76543210 b1-channel data b2-channel data d-channel m-bit x x x x x operation mode command/status bits
delic functional description preliminary data sheet 4-12 2003-08 during initialization the dsp writes a value with '0' in its lsb (other bits are of no importance) to every history ram address associated to an u pn channel that is not to be scrambled, and a value with '1' in its lsb for every u pn channel that must be scrambled. the same values must be written to the descrambler history ram. the hram addresses are: 0x9000 - 0x9017 (scrambler u pn channel 0..23) 0x9020 - 0x9037 (descrambler u pn channel 0..23) for example, in order to activate scrambling and descrambling for channel number 3, the dsp must execute two write operations as follows: write "xxxxxxxxxxxxxxx1" to address 0x9002 write "xxxxxxxxxxxxxxx1" to address 0x9022 these writes are executed only when the scrambler is in idle mode, i.e. value 0x0003 was written by the oak to address 0xd010. 4.2.7.3 s/t mode data is received/transmitted at a nominal rate of 192 kbit/s. each s/t data bit is translated into two bits on iom_2000: data (bit0) and control (bit1). lt-s mode transmit data format lt-s mode receive data format 76543210 b1-channel data b2-channel data d-channel x f a ms x x operation mode command/status bits 76543210 b1 - channel data b2 - channel data d-channel f a xxxxx operation mode command/status bits
delic peb 20571 functional description preliminary data sheet 4-13 2003-08 lt-t mode receive data format lt-t mode transmit data format 76543210 b1-channel data b2-channel data d-channel x f a m s cbn cdi operation mode command/status bits cbn collision detection bit number 0= collision was detected in the first d-bit of the frame 1= collision was detected in the second d-bit of the frame cdi collision detection indication 0 = no collision in d-channel 1 = collision in d-channel detected 76543210 b1-channel data b2-channel data d-channel f a xxxxx operation mode command/status bits
delic functional description preliminary data sheet 4-14 2003-08 4.3 iom-2 unit 4.3.1 iomu overview of features the iomu provides the dsp access to incoming time slots from the iom-2 interface. the dsp may switch the timeslots to the other delic system interfaces. features dsp access for switching of b1 and b2 data to the pcmu and the transiu (providing a constant switching delay of two 8 khz frames) dsp access for extracting of d-channel information dsp access for control of iom-2 command/indication (c/i) and monitor channel information interface configuration two iom-2 ports providing up to 16 iom-2 channels (up to 16 isdn or 32 analog subscribers) available data rate modes: ? two ports of 384 kbit/s each (2 x 6 time slots per frame) ? two ports of 768 kbit/s each (2 x 12 time slots per frame) ? two ports of 2.048 mbit/s each (2 x 32 time slots per frame) ? one port of 4.096 mbit/s (1 x 64 time slots per frame) single or double data rate clock selectable in each data rate mode programmable tri-state control for each port and channel (=4 time slots) push-pull or open-drain configuration drdy signal for d-channel control when connected to quat-s peb 2084
delic peb 20571 functional description preliminary data sheet 4-15 2003-08 4.3.2 iomu functional and operational description figure 4-3 iomu integration in delic 4.3.2.1 frame-wise buffer swapping the main task of the iomu is the serial-to-parallel conversion of incoming iom-2 data to a parallel data format which is directly read by the dsp. this access is required for the dsp to perform switching of b-channels, extraction of d-channels, and layer-1 control via the iom-2 c/i and monitor channels. the data conversion in the iomu is done by frame-wise swapping based on a circular buffer structure. during each 8 khz frame, one buffer is assigned to the iomu (i-buffer), and the other one to the dsp (d-buffer). at the end of every frame, the buffers are swapped. 4.3.2.2 i-buffer logical structure the logical partitioning of each frame buffer into input and output blocks is determined according to the requested data rate as shown in the table below. the address of each data byte in the i-buffer output blocks by the dsp must be selected according to the iom port and time slot index, in which it should be transmitted. delic iomu pcmu hdlcu transiu dsp iom-2 interface dd0 du0 b1 b2 m d,c/i d.c/i m b2 b1 dd1 du1 b1 b2 m d,c/i d.c/i m b2 b1 pcm interface iom-2000 interface switching switching drdy clocks fsc dcl
delic functional description preliminary data sheet 4-16 2003-08 note: in 2 x 384 / 768 kbit/s mode, only the first 6 / 12 bytes of each block are used. 4.3.2.3 dsp access to the d-buffer the d-buffer is mapped to a fixed dsp address space. every dsp access to the d-buffer space is directed automatically to the appropriate sub-buffer. . 4.3.2.4 iom-2 interface data rate modes the iomu may support different serial data rates of the iom-2 interface: 384 kbit/s (6 time slots per frame) 768 kbit/s (12 time slots per frame) 2.048 mbit/s (32 time slots per frame = 8 iom-2 channels per frame) 4.096 mbit/s (64 time slots per frame = 16 iom-2 channels per frame) the iomu circular buffer may handle up to 64 time slots per frame. thus, when in 4.096 mbit/s mode, only iom-2 port 0 is used. in this case iom-2 port 1 remains in idle mode, i.e. the dd1 output pin is tri-stated. note that when using any of the two lower data rates, both iom-2 ports are used. in all data rate modes, single rate data clock (dcl) or double rate data clock may be selected. table 4-3 i-buffer logical memory mapping data rate input blocks output blocks in0 in1 out0 out1 2 x 2.048 mbit/s 2 x 384 kbit/s 2 x 768 kbit/s 00 h - 1f h 20 h - 3f h 40 h - 5f h 60 h - 7f h 1 x 4.096 mbit/s 00 h - 3f h -- 40 h - 7f h -- table 4-4 d-buffer address space data-rate mode d-buffer in0 in1 out0 out1 2 x 6/12/32 time slots/frame 8000 h - 801f h 8020 h - 803f h 8040 h - 805f h 8060 h - 807f h 1 x 64 time slots/frame 8000 h - 803f h -8040 h - 807f h -
delic peb 20571 functional description preliminary data sheet 4-17 2003-08 the iomu meets the iom-2 interface timing specifications as described below. single data rate dcl mode serial transmission via dd0/dd1 with every dcl rising edge sampling of the incoming serial data (du0/du1) with every dcl falling edge sampling fsc with every dcl falling edge. sampling of fsc = 1 after sampling of fsc = 0 is considered to be the start of a frame. double data rate dcl mode two dcl cycles per bit (the bits are aligned to the frame start) serial transmission via du0/1 with every second dcl rising edge. sampling of incoming serial data (dd0/1) with the second dcl falling edge of each bit. sampling of fsc every dcl falling edge. sampling of fsc = 1 after sampling of fsc = 0, is considered to be the start of a new frame. figure 4-4 shows the iom-2 interface timing with single and double rate dcl. for more details refer to the general iom-2 interface description. table 4-5 dcl frequency in different iom-2 modes single/double rate dcl mode iom-2 mode 2x384 kbit/s 2x768 kbit/s 2x2.048 mbit/s 1x4.096 mbit/s single 384 khz 768 khz 2.048 mhz 4.096 mhz double 768 khz 1536 khz 4.096 mhz 8.192 mhz
delic functional description preliminary data sheet 4-18 2003-08 figure 4-4 iom-2 interface timing in single/double clock mode 4.3.2.5 iomu serial data processing the iomu serial data processing is according to the iom-2 specifications. incoming serial data is converted into parallel bytes, and stored in the i-buffer input blocks. the sequence for every time slot received is from msb (bit 7) to lsb (bit 0). transmission is performed in the opposite direction, from msb (bit 7) to lsb (bit 0). 4.3.2.6 iomu parallel data processing the data read from the iomu frame buffers by the dsp always reside in the low byte of the 16-bit word. the high byte of the read word is driven by the 8-bit iomu data prefix register (idpr). the data prefix is used to accelerate the a-/-law to linear conversions (refer to chapter 4.5 ). note: any octet written by the dsp to any location in the iomu frame buffers should reside in the low byte (8 lsb). the high byte of the written word is ?don?t care?. fsc dcl dd0/1 ts31 bit0 ts0 bit7 ts0 bit6 ts0 bit5 ts0 bit4 ts0 bit3 ts0 bit2 ts0 bit1 ts0 bit0 ts1 bit1 du0/1 ts31 bit0 ts0 bit7 ts0 bit6 ts0 bit5 ts0 bit4 ts0 bit3 ts0 bit2 ts0 bit1 ts0 bit0 ts1 bit7 single data rate dcl fsc dcl dd0/1 du0/1 = upstream sampling double data rate dcl frame start = fsc sampling ts31 bit0 ts0 bit7 ts0 bit6 ts0 bit5 ts0 bit4 ts0 bit7 frame start ts0 bit6 ts0 bit5 ts0 bit4 ts31 bit0
delic peb 20571 functional description preliminary data sheet 4-19 2003-08 4.3.2.7 iom-2 push-pull and open-drain modes the iom-2 ports can be configured to push-pull or open-drain modes by a dedicated bit in the iomu control register. when programmed to open-drain, dd0/dd1 is tri- stated when a ?1? is supposed to be transmitted, or during a time slot quadruplet with the associated tri-state register bit set. in both cases the external pull-up resistor, which is used when working in open-drain mode, will ?pull? the value to ?1?. note: when the iomu is programmed to 1x 64 time slots per frame mode, dd1 is tri- stated, independently of the iom-2 interface push-pull or open-drain mode. figure 4-5 iom-2 interface open-drain mode figure 4-6 iom-2 interface push-pull mode iomu delic dd0 dd1 itsr mux mux downstream0 data downstream1 data iomu delic dd0 dd1 itsr mux mux downstream0 data downstream1 data
delic functional description preliminary data sheet 4-20 2003-08 4.3.2.8 support of drdy signal from quat-s the drdy input is used when connecting a siemens quat-s transceiver to the delic via the iom-2 interface. it is driven by the quat-s to inform the delic when a d- channel is occupied by another s-interface device. the iomu supports the synchronous drdy mode, i.e. the quat-s is operated in lt-t mode. in this mode, the drdy signal is valid only during the d-channels. drdy = ?0? means stop (abort hdlc message), and drdy = ?1? means go. figure 4-7 drdy signal behavior iomu drdy support features: sampling drdy only once every d-channel, at the first bit. sampling with the first dcl falling edge (in single data-rate dcl mode), or with the second falling dcl edge (in double data-rate dcl mode), refer to figure 4-8 . drdy support via iom-2 port 0 only (with a constant delay of one 8 khz frame) the status of the drdy line can be read from register idrdyr figure 4-8 drdy sampling timing du0 fsc iom-2 ch 7 d b1 b2 mon iom-2 ch 0 d b1 b2 mon iom-2 ch 1 d b1 b2 mon iom-2 ch 2 d b1 b2 mon iom-2 ch 3 d b1 b2 mon drdy go go stop stop stop = not valid du0 d0 d1 first bit of a d-channel second bit of a d-channel single data-rate dcl drdy valid double data-rate dcl sample point of drdy in single data-rate dcl mode sample point of drdy in double data-rate dcl mode
delic peb 20571 functional description preliminary data sheet 4-21 2003-08 4.4 pcm unit pcm interface features the pcmu enables the dsp to control the 4 pcm ports. the dsp accesses the incoming pcm time slots, and prepares the outgoing pcm time slots. in general, the pcmu enables the dsp to switch time slots from and to the pcm ports. the basic structure and programming model of the pcmu is similar to the iomu. note that the pcmu provides the double capacity of the iomu. thus it may handle up to 4 pcm ports and an overall of 128 time slots per frame in the receive direction and 128 time slots per frame in the transmit direction. the following pcmu data rate modes are available: four streams of 2.048 mbit/s each (single and double clock) two streams of 4.096 mbit/s each (single and double clock) one stream of 8.192 mbit/s (single and double clock) one stream of 16.384 mbit/s (single clock). it is programmable, whether the first or the second 128 time slots of the 8 khz frame are handled in the pcmu. tristate control is performed via pins tsc n, programmable per time slot and port.
delic functional description preliminary data sheet 4-22 2003-08 4.4.1 pcmu functional and operational description figure 4-9 pcmu integration in delic the pcm-unit signals share port pins with the ghdlc-unit. a multiplexer controlled by register muxctrl allows to define the required functionality. 4.4.1.1 frame-wise buffer swapping the main task of the pcmu is the serial-to-parallel conversion of incoming data to a parallel data format (and vice versa) which is directly read by the dsp. this access is required for the dsp to perform switching of b-channels. the data conversion in the pcmu is done by frame-wise swapping based on a circular buffer structure. during each 8 khz frame, one buffer is assigned to the pcmu (i-buffer), and the other one to the dsp (d-buffer). at the end of every frame, the buffers are swapped. 4.4.1.2 dsp inaccessible buffer (i-buffer) the logical partitioning of each frame buffer into input and output blocks is determined according to the requested data rate as shown in the table below. the address of each data byte in the i-buffer output blocks by the dsp must be selected according to the pcm port and time slot index, in which it should be transmitted. pcm unit ghdlc unit hdlc unit transiu dsp oak + memory rxd0, txd0, tsc0 iom unit mux pcm interface rxd1, txd1, tsc1 rxd2, txd2 rxd3, txd3 pdc, pfs tsc2 tsc3
delic peb 20571 functional description preliminary data sheet 4-23 2003-08 note: in 1 x 16.384 mbit/s only the first half of the frame is saved in the buffer 4.4.1.3 dsp accessible buffer (d-buffer) the d-buffer is mapped to a fixed dsp address space. every dsp access to the d-buffer space is directed automatically to the appropriate sub-buffer. table 4-6 i-buffer logical memory mapping of input buffers data rate input blocks in0 in1 in2 in3 related port rxd0 rxd1 rxd2 rxd3 4 x 2.048 mbit/s 00 h - 1f h 20 h - 3f h 40 h - 5f h 60 h - 7f h 2 x 4.096 mbit/s 00 h - 3f h 40 h - 7f h 1 x 8.192 mbit/s 00 h - 7f h 1 x 16.384 mbit/s 00 h - 7f h table 4-7 i-buffer logical memory mapping of output buffers data rate output buffer blocks out0 out1 out2 out3 related port txd0 txd1 txd2 txd3 4 x 2.048 mbit/s 80 h - 9f h a0 h - bf h c0 h - df h e0 h - ff h 2 x 4.096 mbit/s 80 h - bf h c0 h - ff h 1 x 8.192 mbit/s 80 h - ff h 1 x 16.384 mbit/s 80 h -ff h table 4-8 dsp access to d-buffer input blocks data rate input buffer blocks in0 in1 in2 in3 related port rxd0 rxd1 rxd2 rxd3 4 x 2.048 mbit/s a000 h - a01f h a020 h - a03f h a040 h - a05f h a060 h - a07f h 2 x 4.096 mbit/s a000 h - a03f h a040 h - a07f h 1 x 8.192 mbit/s a000 h - a07f h 1 x 16.384 mbit/s a000 h - a07f h
delic functional description preliminary data sheet 4-24 2003-08 note: in 1 x 16.384 mbit/s only the first half of the frame is saved in the buffer 4.4.1.4 pcmu interface data rate modes the pcmu may support different serial data rates: up to 4 ports with 2048 mbit/s (32 time slots per frame) up to 2 ports with 4.096 mbit/s (64 time slots per frame) 1 port with 8.196 mbit/s (128 time slots per frame) 1 port with 16.384 mbit/s (only 128 time slots of the frame are supported) the pcmu circular buffer may handle up to 128 time slots per frame. thus, when e.g. configured in 4.096 mbit/s mode, only pcm port 0 and 2 are used. in this case pcm port 1 and 3 remain in idle mode, i.e. the txd1, txd3 output pins are tri-stated. for the data rate modes up to 8.192 mbit/s, single rate data clock (pdc) or double rate data clock may be selected. for 16.384 mhz mode only single clock is supported. single data rate pdc mode serial transmission via txdn with every dcl rising edge sampling of the incoming serial data (rxdn) with every pdc falling edge sampling pfs with every pdc falling edge. sampling of pfs = 1 after sampling of pfs = 0 is considered to be the start of a frame. double data rate pdc mode two pdc cycles per bit (the bits are aligned to the frame start) serial transmission via txdn with every second pdc rising edge. sampling of incoming serial data (rxdn) with the second pdc falling edge of each bit. sampling of pfs every pdc falling edge. sampling of pfs = 1 after sampling of pfs = 0, is considered to be the start of a new frame. table 4-9 dsp access to d-buffer output blocks data rate output buffer blocks out0 out1 out2 out3 related port txd0 txd1 txd2 txd3 4 x 2.048 mbit/s a080 h - a09f h a0a0 h - a0bf h a0c0 h - a0df h a0e0 h - a0ff h 2 x 4.096 mbit/s a080 h - a0bf h a0c0 h - a0ff h 1 x 8.192 mbit/s a080 h - a0ff h 1 x 16.384 mbit/s a080 h - a0ff h
delic peb 20571 functional description preliminary data sheet 4-25 2003-08 figure 4-4 shows the pcm interface timing with single and double rate pdc. figure 4-10 iom-2 interface timing in single/double clock mode 4.4.1.5 pcmu serial data processing the incoming serial data is converted into parallel bytes, and stored in the i-buffer input blocks. the sequence for every time slot received is from msb (bit 7) to lsb (bit 0). transmission is performed from msb (bit 7) to lsb (bit 0). 4.4.1.6 pcmu parallel data processing the data read from the pcmu frame buffers by the dsp always reside in the low byte of the 16-bit word. the high byte of the read word is driven by the 8-bit pcmu data prefix register (pdpr). the data prefix is used to accelerate the a-/-law to linear conversions (refer to chapter 4.5 ). pfs pdc txd ts31 bit0 ts0 bit7 ts0 bit6 ts0 bit5 ts0 bit4 ts0 bit3 ts0 bit2 ts0 bit1 ts0 bit0 ts1 bit1 rxd ts31 bit0 ts0 bit7 ts0 bit6 ts0 bit5 ts0 bit4 ts0 bit3 ts0 bit2 ts0 bit1 ts0 bit0 ts1 bit7 single data rate pdc pfs pdc txd rxd = data sampling double data rate pdc frame start = pfs sampling ts31 bit0 ts0 bit7 ts0 bit6 ts0 bit5 ts0 bit4 ts0 bit7 frame start ts0 bit6 ts0 bit5 ts0 bit4 ts31 bit0
delic functional description preliminary data sheet 4-26 2003-08 any octet written by the dsp to any location in the pcmu frame buffers should reside in the low byte (8 lsb). the high byte of the written word is ?don?t care?. 4.4.1.7 pcmu tri-state control logic there are eight 16-bit tri-state control registers in the pcmu. each bit determines whether its associated time slot is valid or invalid. '0' = the controlled time slot is invalid '1' = the controlled time slot is valid the tri-state bits control the data transmit pins txd0 - txd3. a special set/reset write method is used for updating the tri-state control registers. every tri-state control register is mapped to 2 addresses: the first is used for set operation, the second for reset operation. both addresses may be used for read operation. set operation: this operation is executed during dsp write access to the set address of one of the tsc registers. the bits in the tsc register are set to '1' according to the bits in the written word. the other bits maintain their value. reset operation: this operation is executed during dsp write access to the reset address of one of the tsc registers. the bi ts in the tsc register are reset to '0' according to the bits in the written word. the other bits maintain their value. the tristate control registers (ptsr0-7) can be accessed by the dsp. every bit of them controls the tsc signal of one of the 4 pcm ports, for one time slot. the time slot and the port controlled by every bit depend on the data rate mode. in 1x256 ts/frame, it depends also on the selected half of the frame. each tsc signals controls directly its respective txd port, and is also driven outward via the corresponding tscn output pin. for the 4 x 32 time slot per frame mode, the next table depicts which port is controlled by each tsc register, and during which time slot. bit 0 of each tsc register controls the first time slot of the listed time slot range, bit 1 controls the second one etc. in 2 x 64 time slot per frame mode, only pcm ports 0 and 2 are used. tsc1 and tsc3 are permanently '0' (all time slots are invalid). table 4-10 pcm tsc in 4 x 32 ts mode time slots tsc0 tsc1 tsc2 tsc3 0..15 ptsc0 ptsc2 ptsc4 ptsc6 16..31 ptsc1 ptsc3 ptsc5 ptsc7
delic peb 20571 functional description preliminary data sheet 4-27 2003-08 in 1 x 128 time slot per frame mode, only pcm port 0 is used. tsc1, tsc2 and tsc3 are permanently '0' (all time slots are invalid). in 1 x 256 time slot per frame mode, only one half of the frame is used. all tsc pins are permanently '0' during the other half of the frame. note: the same structure applies to the 256 ts per frame (first frame half) mode, except that all time slots (0..127) are transmitted in the first half of the 8 khz frame. table 4-11 pcm tsc in 2 x 64 ts mode time slots tsc0 tsc1 tsc2 tsc3 0..15 ptsc0 inactive ptsc4 inactive 16..31 ptsc1 inactive ptsc5 inactive 32..47 ptsc2 inactive ptsc6 inactive 48..63 ptsc3 inactive ptsc7 inactive table 4-12 pcm tsc in 1 x 128 ts and 1 x 256 ts (1st half) mode time slots tsc0 tsc1 tsc2 tsc3 0..15 ptsc0 inactive inactive inactive 16..31 ptsc1 inactive inactive inactive 32..47 ptsc2 inactive inactive inactive 48..63 ptsc3 inactive inactive inactive 64..79 ptsc4 inactive inactive inactive 80..95 ptsc5 inactive inactive inactive 96..111 ptsc6 inactive inactive inactive 112..127 ptsc7 inactive inactive inactive table 4-13 pcm tsc in 1 x 256 ts (2nd half) mode time slots tsc0 tsc1 tsc2 tsc3 0..127 inactive inactive inactive inactive 128..143 ptsc0 inactive inactive inactive 144..159 ptsc1 inactive inactive inactive 160..175 ptsc2 inactive inactive inactive 176..191 ptsc3 inactive inactive inactive 192..207 ptsc4 inactive inactive inactive
delic functional description preliminary data sheet 4-28 2003-08 208..223 ptsc5 inactive inactive inactive 224..239 ptsc6 inactive inactive inactive 240..255 ptsc7 inactive inactive inactive table 4-13 pcm tsc in 1 x 256 ts (2nd half) mode time slots tsc0 tsc1 tsc2 tsc3
delic peb 20571 functional description preliminary data sheet 4-29 2003-08 4.5 a-law/-law conversion unit the a-/-law unit performs a bi-directional conversion between a linear representation of voice data and its companded representation (according to a-law or -law ). the conversion is possible for all b-channels transceived via iom-2, iom-2000 or pcm. a-/-law to linear conversion the conversion is done via a 512 x 16 rom table. the low 256 bytes translate the a-law value into linear, while the high 256 words translate the -law to linear. the dsp issues a read cycle, in which the 8 msbs of the 16-bit address represent the rom table address, and the 8 lsbs are the actual value which is to be converted. the converted linear value is the contents read from the rom. note that no wait states are required for this direction of conversion. a-law values in the rom are stored in the 13 msbs. the 3 lsbs are always '0'. the - law values in the rom are stored in the 14 msbs. the 2 lsbs are always '0'. linear to a-/-law conversion the conversion is done by dedicated hardware. the dsp programs the control register to perform either a-law or -law conversion. the linear value is written into the input register (amir), and the a-law or -law value is read from the output register (amor). note that this is only possible one cycle later.
delic functional description preliminary data sheet 4-30 2003-08 4.6 hdlc unit 4.6.1 hdlcu unit overview the hdlcu decodes and encodes hdlc messages to and from the dsp. it may process up to 32 full-duplex hdlc channels in parallel. it is controlled by the dsp through software and is thus very flexible. the hdlcu includes a receive input buffer, a receive output buffer, a transmit input buffer and a transmit output buffer, some hdlc protocol processing logic and a command ram. figure 4-11 hdlcu general block diagram figure 4-11 shows the hdlcu structure. each buffer, except the transmit output buffer, is a 32 x 8 ram, hence one byte is assigned to each hdlc time slot channel. receive output buffer transmit input buffer receive input buffer transmit output buffer 32 channels 32 channels 32 channels 32 channels processing internal command ram dsp control dsp data double buffer dsp data double buffer encoded decoded 32x8 32x16 32x8 32x8 32x8 dsp d-buffer* dsp d-buffer* processing internal * frame-buffers of the iomu, pcmu or transiu that belong to the dsp during the present frame
delic peb 20571 functional description preliminary data sheet 4-31 2003-08 the transmit output buffer is a 32 x 15 ram because, in addition to each hdlc channel, there is also a 7 bit status vector assigned to each channel stored in this buffer. the dsp assigns each time slot used for transceiving an hdlc message to a different address in the receive/transmit input buffers. the hdlcu decodes/encodes the time slots into the corresponding addresses in the receive/transmit output buffers. during every frame, two hdlcu activities are performed: 1. dsp access to the hdlcu 2. hdlcu encoding/decoding at the beginning of a frame the dsp checks if the hdlcu is busy (hhold = ?0?). note that the dsp may only access the buffers and command ram when dspctrl = ?1?. in the receive direction the dsp places hdlc message time slots to be processed from the d-buffers into the receive input buffer. processed message time slot octets may be read by the dsp from the receive output buffer. in the transmit direction the dsp places hdlc message time slots to be processed in the transmit input buffer. processed time slots may be read from the transmit output buffer and placed into the d-buffer of the iomu, pcmu or transiu from which they will be transmitted during the next frame. 4.6.2 dsp operation of the hdlcu 4.6.2.1 initialization of the hdlcu the first frame is used to reset the receive and transmit mechanisms of each channels. 1. the dsp asks for the hdlcu setup from the external controller. 2. the dsp sets the bit dspctrl to ?1?. 3. the dsp resets the receive mechanism and transmit mechanism of a channel by setting the recres flag of its command vector to ?1? and inserting an abort command. the dsp also writes the setup of the hdlcu. 4. the dsp sets dspctrl to ?0?. 5. when the hdlcu finishes processing (hhold = ?1?), the hdlcu is initialized and is ready for use. 4.6.2.2 transmitting a message in order to transmit a message the dsp must place a start transmission command in the appropriate address in the command ram. if crc encoding is required, then the dsp must set bit 1 to ?1? in the command vector. in the unshared flag mode, during the first frame a flag is transmitted over the channel. after the flag has been transmitted, the hdlcu starts to transmit the message. in the
delic functional description preliminary data sheet 4-32 2003-08 shared flag mode the hdlcu starts transmitting the message in the frame adjacent to the reception of the start transmission command. note: messages with zero byte data content are not supported. 4.6.2.3 ending a transmission when placing the last octet of the message into the transmit input buffer, the dsp should place an end transmission command in place of the start transmission command without changing the crc bit. if crc encoding is required, the crc vector will be transmitted bit by bit after the octet of the message, and then a flag will be transmitted. if crc encoding is not required, a flag will be transmitted directly after the last octet of the message. note that in unshared flag mode, if no adjacent frame exists, ?ones? will be transmitted after the flag. 4.6.2.4 aborting a transmission in order to abort transmission of a message over a dedicated channel, the dsp places an abort command in the appropriate address in the command ram. the message being transmitted over the channel is aborted and ?ones? are transmitted over the channel instead (even in the shared flag mode). 4.6.2.5 dsp access to the hdlcu buffers reading a channel from the receive output buffer and writing to a channel in the transmit input buffer is done according to the channel status vector and according to the empty and full procedures as shown below: empty procedure if the empty flag of a channel is set by the hdlcu to ?1?, then move a new time slot to be transmitted from the pipe to the transmit input buffer. if the pipe is empty change the pipe page and ask for the next 16 bytes of data from the external controller by means of dma or interrupt. note: the b-channel buffer may be emptied within a single frame, while it takes at least 4 frames to empty a d-channel buffer. full procedure if the full flag of a channel is set by the hdlcu to ?1? then the dsp moves the time slot from the receive output buffer into the double buffer. if the pipe is full change the pipe page and transfer the next 16 bytes of data to the external controller by means of dma or interrupt. note: the b-channel buffer may be filled within a single frame, while a d-channel buffer will take at least 4 frames to fill.
delic peb 20571 functional description preliminary data sheet 4-33 2003-08 reading data from the receive output buffers when the dsp reads a time slot from an even address in the receive output buffer, the hdlcu will place it on the lsb byte of the data bus and ?0? on the msb byte. when the dsp reads a time slot from an odd address, the hdlcu will place it on the msb byte of the data bus and ?0? on the lsb byte. writing data to the transmit input buffers when the dsp writes to an even address in the transmit input buffer, the hdlcu will write the lsb of the data bus. when the dsp writes to an odd address, the hdlcu will write the msb byte of the data bus.
delic functional description preliminary data sheet 4-34 2003-08 4.7 ghdlc unit 4.7.1 ghdlc overview the ghdlc (general hdlc) controls the dedicated serial communication interface of the delic. the purpose of the ghdlc is to decode incoming hdlc messages and to encode outgoing messages according to the hdlc protocol. the ghdlc transceives hdlc data streams with up to 16.384 mbit/s. a received message is collected bit by bit from the line and stored as octets in the receive buffer and read by the dsp. a transmitted message which is placed by the dsp as octets in the transmit buffer, is transmitted bit by bit over the line. . figure 4-12 data processing in the ghdlc 4.7.2 ghdlc channel external configurations the ghdlc line interface may be connected to other ics in three different ways: point-to-point point-to-multi-point multi-slave 4.7.3 ghdlc general modes the ghdlc provides three main modes of operation: hdlc mode: in this mode flag recognition/insertion, zero deletion/insertion and crc decoding/encoding are performed. asynchronous mode: this mode is used with request-to-send / clear-to-send handshaking. in this mode data is transmitted at a very slow rate of up to 300 baud and controlled directly by the dsp. receive buffer transmit buffer receive processing transmit processing data in from line data out to line bit by bit double buffer double buffer bit by bit dsp dsp command vector set-up vectors status and interrupt vector lrxd ltxd
delic peb 20571 functional description preliminary data sheet 4-35 2003-08 4.7.4 ghdlc protocol features the following ghdlc features related to the hdlc protocol may be selected in hdlc mode: collision detection: may be active or inactive (relates only to the transmit direction) flags / ones interframe: flags or ones are transmitted between each frame (relates to both the transmit and receive direction) note that transmitted messages always use unshared flags. shared / unshared flag: in shared flag mode only one flag separates adjacent messages (relates only to the receive direction) crc mode: three possible settings: 16-bit crc / 32-bit crc / no crc (relates to both the transmit and receive directions, and only when operating in the hdlc mode). push-pull / open drain: in push pull mode a pin may be driven to ?1? or ?0?. when in open drain mode a pin may be driven to ?0? or high z. 4.7.5 external configuration and handshaking in bus mode the ghdlc is connected to the following delic interface lines: figure 4-13 ghdlc interface lines serial data is transceived over the lrxd/ltxd lines. the line clock can be driven by an external ghdlc device or can be generated internally by the pcm clocking path. the selected internal clock is also driven outward via lclk. 4.7.5.1 external tri-state in point-to-multi-point mode ltsc is the external tri-state control line. when ltsc is high ltxd is disabled and in high impedance state. when ltsc is low, ltxd may take on values 0 or 1 when in push pull mode, 0 or high impedance when in open drain mode. ghdlc ltxd ltsc lrxd lcxd / cts / rts lclk
delic functional description preliminary data sheet 4-36 2003-08 4.7.5.2 arbitration of ghdlcs on a collision bus several ghdlc channels (in a point to multi-point configuration) may be connected to an external signaling backplane. arbitration between them may be done in two ways: polling or collision detection. in polling mode the ghdlc master (in a point to multi-point configuration) is responsible to prevent collisions on the line. in this case a delic-slave has to be polled by the ghdlc-master with a special requesting frame. the delic ghdlc-unit simply receives this frame and passes it to the p (like any other frame). now it?s the task of the p to handle the message and provide a corresponding answer message. when using collision detection many ghdlcs may start transmitting at the same time. if the ghdlc detects a difference between the transmitted bit (ltxd) and the collision bit (lcxd), the transmission is aborted. the ghdlc will try to send the message again after the bus was detected idle for a specified time, according to its priority class (refer to itu-t i.430, section 6.1.4). 4.7.6 ghdlc memory allocation the memory in the ghdlc is build by a 128x8 bit ram equally divided between the ghdlc and the dsp. the ghdlc has a receive buffer and a transmit buffer, divided into two blocks. one block is allocated to the ghdlc channel in the receive direction, the other block is read by the dsp. similarly in the transmit buffer, one block is allocated to the ghdlc channel in the transmit direction, the other block is written to by the dsp as shown in figure 4-14 . note that the ghdlc has higher priority for the buffer access, whereas the dsp is able to read and write the ram at a much higher frequency. in the receive direction blocks are swapped in two cases: the receive buffer is full. the swap is issued immediately after the buffer has become full. an end of a frame indication was detected at the beginning of a fsc-frame. to avoid a loss of data in case of a buffer full indication followed by an end of frame indication, this condition becomes only true if additionally there was no full interrupt during the previous frame. in the transmit direction blocks are swapped each time a start transmission command is issued in the command register.
delic peb 20571 functional description preliminary data sheet 4-37 2003-08 figure 4-14 ghdlc receive and transmit buffer structure the ghdlc unit and dsp always read and write to different areas in the ram. memory is equally allocated to each of the receive and transmit buffer blocks (32 bytes each). the dsp always writes to the block addresses. the switching between blocks is done internally and does not concern the dsp. 4.7.7 ghdlc interrupts full interrupt: a full interrupt is generated if: the receive buffer is full. the interrupt is issued immediately after the buffer has become full. an end of a frame indication was detected at the beginning of a fsc frame. to avoid a loss of data in case of a buffer full indication followed by an end of frame indication, this condition becomes only true if additionally there was no full interrupt during the previous frame. empty interrupt: an empty interrupt is generated every time a transmit buffer was emptied by the ghdlc. note: messages with zero byte data content are not supported. ghdlc receive dsp read block block receive buffer ghdlc transmit dsp write block block transmit buffer
delic functional description preliminary data sheet 4-38 2003-08 4.8 dsp control unit 4.8.1 general the dcu controls the dsp access to delic?s blocks. it performs the following tasks: dsp program and data address decoding interrupt handling data bus and program bus arbitration dsp run time statistics boot support emulation support 4.8.2 dsp address decoding the dcu decodes the dsp data address bus (dxap) and the dsp program address bus (ppap) for performing the following tasks: generating the dsp memory mapped register controls, based on decoding of the 8 msb lines of the data address bus generating the ghdlc, transiu, hdlcu, iomu and pcmu ram controls generating program and data ram controls upon detection of their address generating the read signal for the program rom 4.8.3 interrupt handling the following events are reported by the various telecom peripheral blocks to the dsp: ghdlc dma mailbox p mailbox iom interface frame synchronization (fsc) interrupt pcm interface frame synchronization (pfs) interrupt the ghdlc, dma mailbox and microprocessor mailbox interrupt sources are assigned to the dsp interrupts (int0, int1 and int2) as shown in table 4-14 . the fsc and pfs are reported as status bits (require dsp polling) in the status event register (steve). table 4-14 interrupt map interrupt source int0 p dma mailbox int1 p general mailbox int2 fsc & pfs nmi ghdlc
delic peb 20571 functional description preliminary data sheet 4-39 2003-08 note: the nmi interrupt maybe enabled/disabled in the intmask register. 4.8.4 dsp run time statistics the dsp run time statistics is used for the dsp work load estimation. by using this hw, the maximum time spent by the dsp from the fsc until the tasks ends may be found. the dsp statistics include an eight bit counter statc which is counting up every 1 s. figure 4-15 statistics registers statc is reset upon fsc rising edge. when the dsp finishes a task, it reads statc. the time between two consecutive fsc is always 125 s, therefore, if the dsp is working properly, the counter value should always be less then 125 s. if the dsp failed to read the counter value and a new fsc rising edge has arrived, the counter is not reset. therefore, the dsp reads a value greater then 125. it means that the dsp failed to finish it?s tasks within the time frame of 125 s. the stati register is added for helping the user to perform the statistics. stati is a general purpose 8-bit read/write register. the user program should perform statistics in the following way: ? the statc is reset upon detection of fsc rising edge. ? the dsp finishes its activities and reads the value of statc and stati. the dsp compares statc to the previous maximum value saved in stati. ? if the new value is larger, it is written to stati. the system programmer can get the counter value via p mailbox and thus can change the dsp program. 1 s dsp reset by fsc of the frame n+1, only if statc the dsp has read the counter already dsp maximum value register counter (in frame n) stati
delic functional description preliminary data sheet 4-40 2003-08 4.8.5 data bus and program bus arbitration the internal data bus (gexdbp) and program data bus (gip) are tristate buses. since these buses must never float, the dcu keeps track of the bus activities. if during a dedicated cycle no driver is on the bus, the dcu puts a default value on the bus. 4.8.6 boot support the p boot is the process which loads the external p program ram via the p mailbox into the on-chip dsp program ram. the boot is controlled by a boot routine residing in the internal dsp program rom. this routine is started upon delic reset according to the boot strap pin status. the second boot option is the emulation boot, which loads the monitor (bi routine) to the program ram. this routine enables the pc emulator to control the dsp. at system start-up the program code for the dsp is transferred into the internal ram from the external up. the contents for the program and data boot is delivered in a so called hex file. the code format of the hex file is the following: code,:,16 bit address, 16 bit opcode c:0000 4180 c:0001 0018 c:0004 4180 c:0005 00ba c:0006 4180 c:0007 00bd c:000e 4180 c:000f 00be ... the program boot starts with the "start loading program ram" command which is coming from the delic boot routine. ocmd = 0x1f this command must be polled from the up because the interrupt is still not activated. the up confirms this with the "start boot" command. mcmd = 0x55 the program code is now transferred in pieces of maximum 15 words by use of the "write program memory command". mdt0 = 0xdestination_address mdtn = 0xopcode_wordn mcmd = 0xan [n=1..15 number of code words to write to address++]
delic peb 20571 functional description preliminary data sheet 4-41 2003-08 before writing this command, the up must check that the mailbox is free. this is done by reading the mbusy bit (bit 7 of address 0x41). the up must wait until this bit is reset before sending the next command. missing addresses in the hex file must not be loaded. the "write program memory command" must be repeated until the program code is fully loaded. the end of the code segment inside the hex file is the change from c: (code) to d: (data). this is the start of the data segment, which is needed for the data boot, described in the next step. after all the code has been loaded, the "finish boot" command must be sent: mcmd = 0x1f 4.8.7 reset execution and boot strap pin setting the reset is executed via low signals on the delic reset pin (29) and the vip reset pin (44). it is recommended to connect the vip reset inputs to the delic resind output pin (89). the resind signal is a delayed reset signal and stays at least 500 us after termination of the delic reset input. this mechanism ensures that all output clocks of the delic have become stable even after a short reset was applied. connecting the vip reset to this resind signal ensures stable vip clocking after reset (layer1 clock, dcl2000, fsc). together with applying the reset signal to the delic, the strap pin signals must be defined. there are 9 pins at the delic device which have a special functionality. these so called strap pins are used as inputs while reset is active and determine different modes like master/ slave mode of the pcm interface, test modes, boot mode,... please refer to page 2-28 for detailed information about the strap pin options. the settings of the strap signals are sampled with the rising edge of the delic reset input signal. for a up- boot, the default settings of strap 4 (emulation boot) and strap 6 (boot strap) are needed. after a correct reset execution and strap pin setting, the delic sends the command "start loading program ram" to the up: ocmd = 0x1f
delic functional description preliminary data sheet 4-42 2003-08 4.9 general mailbox 4.9.1 overview the p and the dsp communicate via a bidirectional mailbox according to the mailbox protocol described in chapter 11 . the delic provides two dedicated mailboxes that may be used in two operational modes: dma mode in which the two mailboxes operate independently, one serves as a general purpose mailbox and the other serves as a dma mailbox. expanded mailbox mode in which the two mailboxes are regarded as a enlarged general purpose mailbox, providing a double number of registers. the general purpose mailbox includes two separate parts: p mailbox - enables transfers from the p to the oak. oak dsp mailbox - enables transfers from the oak to the p. both parts include a command register, 9 x (16-bit) registers (17 registers in expanded mode) and a busy bit. one of the data registers in every part has a special addressing mode, i.e. the oak may access either a certain byte of a word or the whole word which is temporarily stored in the mailbox. this requires to use 3 different addresses in oak?s direction. note: the mailbox protocol commands structure is described in chapter 11 . 4.9.2 p mailbox the p mailbox includes: eight 16-bit data registers (mdtn) a16-bit general register (mgen) an 8-bit command register (mcmd) a 1-bit busy register (mbusy) registers mdtn, mgen and mcmd may be written by the p and read by the oak. the mbusy register may be written by the dsp and read by the p. a write of the p to the mcmd-register of the p-mailbox generates an interrupt to the oak. thus, the user has to provide all mailbox data prior to writing to register mcmd. the mbusy bit which may be read by the p (register mbusy) is set automatically after a write to the p command register (mcmd) and reset automatically by a direct oak write operation to it. note: the command opcodes are defined in chapter 11 . data transfer from the p to the oak the p reads the busy bit and checks whether the mailbox is available (mbusy=?0?)
delic peb 20571 functional description preliminary data sheet 4-43 2003-08 the p writes to the data registers mdtn(optional) the p writes to the p command register (mcmd), this write must be performed and sets automatically the p mailbox busy bit (mbusy). an oak interrupt (int2) is activated due to the write to the command register (mcmd). the oak int2 routine reads mcmd and performs the command (the read of the command register resets the int2 activation signal). when finished, the int2 routine resets mbusy for enabling the p to send the next command. note: the p may perform consecutive writes to the p mailbox, and the user must guarantee that the data has been transferred to the oak correctly (the busy bit has been reset) before writing new data to the p mailbox. 4.9.3 oak mailbox the oak mailbox includes: eight 16-bit data registers (odtx) a 16-bit general register (ogen) an 8-bit command register (ocmd) a 1-bit busy register (obusy) registers odtx, ogen and ocmd may be written by the oak and read by the p. the obusy bit may be written by the p and read by the oak. in addition, the p can read this bit (because the p could poll this bit). a write of the oak to register ocmd of the oak mailbox generates an interrupt to the p. thus the oak firmware provides all mailbox data prior to writing to register ocmd. the obusy- bit which can be read by the oak, is set automatically after a write of the oak to register ocmd and is reset by a direct p write to it (when the p has finished reading the oak mailbox contents). note: the opcodes indications are defined in chapter 11 . data transfer from the oak to the p the oak reads the busy bit and checks whether the mb is available (obusy=?0?) the oak writes to the data registers odtn (optional) the oak writes to the command register (ocmd). this write must be performed and automatically sets the oak mailbox busy bit (obusy) a p interrupt is activated due to the write operation to the register ocmd. the p reads the command register and performs the command. when finished, the p resets obusy for enabling the oak to send the next command.
delic functional description preliminary data sheet 4-44 2003-08 note: the oak may perform consecutive writes to the oak mailbox and the oak firmware guarantees that the data has been transferred to the p correctly (obusy has been reset) before writing new data to the oak mailbox.
delic peb 20571 functional description preliminary data sheet 4-45 2003-08 4.10 dma mailbox 4.10.1 overview this mailbox is used for dma transfers of data in ?memory-to-memory? or ?flyby? modes. in a special mode, it may be used as an extension to the general purpose mailbox. the transfer is done similarly to the general mailbox, with some differences: 1. there are 2 configurations: dma, and secondary mailbox. 2. the master of the transfer in dma mode is always the oak. the dma mailbox includes two separate parts: transmit ( p) mailbox for fast transfers from the dma (p) to the ghdlc (oak). receive (oak) mailbox for fast transfers from the ghdlc (oak) to the dma (p). in transactions between p and oak the later indicates when it is ready for transmit / receive operation by driving dreqt/dreqr high, and p replies by driving dack low. dack acts like a chip select signal and remains low during the whole transaction. by driving dack high the dma may stop the transaction on any stage, even if the data transfer has not finished yet. there are two possible modes in dma transfers: memory-to-memory and flyby. selecting these modes is done by writing ?1? or ?0? to the configuration register. the mode of dma?s operation depends on the p that initiates a dma transfer (intel/ siemens or motorola). this mode information is provided via the mode input pin of the delic. the number of bytes (words) to be transferred is written to tx_creg and copied to tx_count. after finishing a transaction, int1 is issued to the dsp in order to indicate that the mailbox is empty and available for the next operation. 4.10.2 intel/siemens mode and motorola mode (memory-to-memory) in intel/siemens mode the control lines are dack , rd , wr . driving rd low when dack is low causes a ?read? from the mailbox. driving wr low when dack is low causes a ?write? to the mailbox. in motorola mode the control lines are dack , r/w , ds . driving r/w high when dack and ds are low causes a ?read? from the mailbox. driving r/w low when dack and ds are low causes a ?write? to the mailbox. 4.10.3 fly-by mode in fly-by mode dma transfer is done in one bus transaction. the dma should provide a ?read? command to the mailbox and, at the same time, a ?write? command to the system memory (or a ?write? to the mailbox and a ?read? to the memory). the system memory
delic functional description preliminary data sheet 4-46 2003-08 must always get a ?write? command for a write operation or a ?read? for a read operation. the mailbox, however, reacts in the opposite way: it writes (puts data into a register) upon receiving a ?read? command and reads (drives data on the bus) upon receiving a ?write? command. 4.10.4 pec mode the additional mode which is possible in work with some siemens ps is pec mode. in this case dma controller is edge sensitive, so edges are provided on dreq lines in order to initiate every dma transfer. 4.10.5 transmit mailbox the transmit mailbox includes: 18-byte fifo which is accessed by the oak (for read) as 9 ?regular? addressed 16- bit-wide registers and by the dma (for write) like a fifo. one of the nine registers is a ?special? register like in the general mailbox and has 3 addresses associated with it. 5-bit counter for the general number of transactions in current transfer (tx_creg) 5-bit counter for the number of transactions that remains in the transfer (tx_cnt). 1-bit status register (tx_stat). the oak is always the master of this transfer, i.e. the transfer is initiated b the oak, but the functions of control and arbitration during the transfer are done by the dma. for dma request , the oak requests transfer of data to the high-speed ghdlc channel. it writes the number of bytes needed to the tx_creg register which sets tx_bsy bit, and causes the assertion of dreqt (?dma request transmit?) pin. for dma acknowledge , the dma grants the bus to oak by driving dack low, and begins toggling the control lines. in intel/siemens (mem-to-mem) mode it drives the wr line low when it writes to the mailbox, and high when it reads from the memory on the second side. rd line stays high during the complete transfer, because there are no ?read? operations from here. dack is low all the time. in motorola (mem-to-mem) mode it drives r/w line low for ?write? operations when dack and ds are low; when dma refers to the external memory, it drives ds high. note that in fly-by mode the meaning of ?read? and ?write? commands is opposite for the mailbox. after every ?write? operation the counter (tx_cnt) is decremented by one. if the dma stops the transaction before finishing, it has to drive dack high. the oak continues driving dreqt high, stops decrementing tx_cnt and waits until dack becomes low. after a write of tx_creg bytes by the dma to the transmit mailbox, the tx_cnt becomes ?0?. then tx_bsy bit is reset to ?0?, and dreqt is deasserted. a reset of tx_bsy bit may be programmed to generate an interrupt (int1) to the oak. the oak will then read tx_creg bytes from the mailbox to the ghdlc, the first byte being the lsb of the least significant word of the fifo. note that in case of an odd
delic peb 20571 functional description preliminary data sheet 4-47 2003-08 number of bytes to be transferred the last byte is available on the least significant byte of the last word in fifo. note: tx_bsy is not an indication for the transaction partners. it may be used for internal software needs of the oak. data transfer via the transmit mailbox the oak writes to tx_creg. dreqt is asserted (?high?), and tx_bsy bit is set (?1?). the dma asserts dack = 0 and issues tx_creg write transactions to the mailbox. dreqt is deasserted (?low?), and tx_bsy bit is reset (?0?). if tx_mask bit is reset (?0?): an oak interrupt (int1) is activated. the oak reads the tx_reg bytes in the mailbox and transfers them to the ghdlc. note: 1. the oak must not write to the tx_creg reg before tx_bsy is reset. 2. writing?0? to tx_creg is not allowed. 4.10.6 receive mailbox the receive mailbox includes: 18-byte fifo which is accessed by the oak (for write) as 9 ?regular? addressed 16- bit wide registers, and by the dma (for read) like a fifo. one of the nine registers is a ?special? register like in the general mailbox and has 3 addresses associated with it. 5-bit counter for the general number of transactions in current transfer (rx_creg). 5-bit counter for number of transactions that remains in the transfer (rx_cnt). 1-bit status register (rx_stat). like in the transmit mailbox, the oak is always the master of this transfer, i.e. the transfer is initiated by the oak, but controlled by dma. when the oak requests a transfer of data from the high-speed ghdlc channel, it writes this data to the receive mailbox, the first byte to the least significant byte of the least significant word. note that in case of odd number of bytes, the most significant byte of the last word is don?t care. then, the oak writes the number of bytes needed to the rx_creg register which sets rx_bsy bit, and causes the assertion of dreqr (?dma request receive?) pin. if dma grants the bus to oak, it drives dack low and begins toggling the control lines. in intel/siemens (mem-to-mem) mode it drives rd line low when it reads from the mailbox and high when it writes to the memory. wr line stays high during the complete transfer, because there are no ?write? operations from here. dack is low all the time. in motorola (mem-to-mem) mode it drives r/w line high for ?read? operations when dack and ds are low; when dma refers to the external memory, it drives ds high. note that in fly-by mode the meaning of ?read? and ?write? commands is opposite for the mailbox. after each ?read? operation the counter (rx_cnt) is decremented by one. if
delic functional description preliminary data sheet 4-48 2003-08 the dma stops the transaction before finishing, it has to drive dack high. the oak continues driving dreqr high, stops decrementing rx_cnt and waits until dack becomes low. after a read of rx_creg bytes by the dma from the receive mailbox, the rx_cnt becomes ?0?. then rx_bsy bit is reset to ?0?, and dreqr is deasserted . reset of rx_bsy bit may be programmed to cause an interrupt (int1) to the oak. note: rx_bsy is not an indication for the transaction partners. it may be used for internal software needs of the oak . data transfer via the receive mailbox the oak writes rx_creg bytes to receive mailbox. the oak writes to rx_creg. dreqr is asserted (?high?), and rx_bsy bit is set (?1?). the dma asserts dack and issues rx_creg read transactions to the mailbox. dreqr is deasserted (?low?), and rx_bsy bit is reset (?0?). if rx_mask bit is reset (?0?): an oak interrupt (int2) is activated. note: 1. the oak must not write to the rx_creg reg before rx_bsy is reset. 2. writing ?0? to rx_creg is not allowed. 4.10.7 access to the dma fifos the size of the fifos is 18 bytes (9 words) for each tx and rx. on the oak side, each fifo contains 9 registers (tdt0-8 and rdt0-8) which may be accessed separately. on the dma side, only the current top of the fifo is available. the transfer is divided to bulks, the size of the current bulk is determined in the rx_creg/tx_creg. transmit fifo this fifo is written by the dma. the first write in a bulk will be to tdt0 least significant byte, the second to tdt0 most significant byte, etc., until the size of the current bulk was reached. then the oak will read the data from the relevant tdtn registers. receive fifo this fifo is written by the oak. the oak fills rdt0 to rdtn. the dma will then read consecutive bytes from the fifo, where the first byte will be rdt0 least significant byte, the 2nd rdt0 most significant byte, etc. until the size of the current bulk was reached. note: this rx fifo and tx fifo functionality is only provided when the mailbox is in dma mode (cfg:dma = ?1?). in case of non dma mode (cfg:dma = ?0?), the fifos are used as secondary (extension) to the general purpose mailbox, which means that the general purpose mailbox will have 18 words for each direction (oak and p), instead of 9.
delic peb 20571 functional description preliminary data sheet 4-49 2003-08 4.11 dsp core oak+ the delic integrates an oak+ dsp core, an enhanced version of the oak. it is clocked using an on-chip pll at a frequency of 61.44 mhz. it may also be driven by lower clock rates provided by an external oscillator. the oak+ is a high performance fixed-point dsp with a 16-bit data and program bus. due to an optimized cost-performance rate, it is widely used not only in line cards and pbx applications, but also in cellular phones, fast modems, advanced fax machines, and answering machines. the core?s main block is a high performance central processing unit, including a full- featured bit manipulation unit, ram and rom addressing units, and program control logic. all other application specific peripheral blocks, are defined as part of the user on- chip logic. the oak+ provides an advanced set of dsp and generic microprocessor functions for straightforward generation of efficient and compact code. for more details on oak architecture please refer to ?doc dsp programmer?s reference manual, 11.97?.
delic functional description preliminary data sheet 4-50 2003-08 4.12 clock generator 4.12.1 overview the delic clock generator provides all ne cessary clock signals for the delic and connected clock slave devices. the internal clocks are generated by two on-chip plls: 1. a digital controlled oscillator (dcxo) generates a 16.384 mhz clock from an external crystal. 2. a pll multiplies the 16.384 mhz clock to a 61.44 mhz clock. an overview of the clock signals and a block diagram is shown below. table 4-15 overview of clock signals pin function i/o during reset clk16-xi 16.384 mhz external crystal input i i clk16-xo 16.384 mhz external crystal output o o xclk external reference clock from layer-1 ic (2.048 mhz, 1.536 mhz or 8 khz) ii (1.536 mhz) refclk pcm reference clock (8 khz or 512 khz) i/o tristate pfs pcm frame synchronization 8 khz (i/o) or 4 khz (i) i/o i (slave) o (master) pdc pcm data clock (2.048, 4.096, 8.192 or 16.384 mhz) i/o i (slave) o (master) (2.048 mhz) clkout auxiliary clock (2.048, 4.096, 8.192, 16.384, or 15.36 mhz) oo (2.048 mhz) dcl_2000 iom-2000 data clock (3.072, 6.144 or 12.288 mhz) o o (3.072 mhz) dcl iom-2 data clock (384 khz, 768 khz, 2.048 mhz or 4.096 mhz) oo (384 khz) fsc iom-2 and iom-2000 frame synchronization 8 khz. o o l1_clk layer-1 clock 15.36 or 7.68 mhz (e.g. octat-p / quat-s) oo (7.68 mhz) dsp_clk dsp test clock. (to run the dsp at clock rates other than 61.44 mhz) ii
delic peb 20571 functional description preliminary data sheet 4-51 2003-08 figure 4-16 delic clock generator 61.44 :2 15.36 mhz :8 mux dsp clk 8 khz delic pd pll 16.384 mhz mux 6.144 mhz dcl_2000 12.288 mhz :20 pdc dcl pfs m/s 3.072 mhz :2 7.68 mhz :1 dcxo clk16-xi clk16-xo filter 16.384 mhz :2 m/s(strap :64 :1 512 khz / 8 khz refclk shp short fsc (fallback) dsp_clk (reference clock :2 :15 :30 :2 :256 :512 fsc 8 khz clkout 2.048 mhz 4.096 mhz :2 :2 :256 8.192 16.384 mhz mhz 4.096 mhz 2.048 mhz 8 khz 2.048 mhz 4.096 mhz 8.192 mhz 16.384 mhz mux xclk (reference clock from l1 device, 1.536 mhz or 2.048 mhz or 8 khz) pcm) :192 :256 :1 8 khz 8 khz refs :3 :4 :192 :256 8 khz :10 :5 mhz :1 :2 l1_clk :80 :160 384 khz 768 khz :48 :96 lclk mux ghdlc 1.536 mhz 15.36 mhz option)
delic functional description preliminary data sheet 4-52 2003-08 4.12.2 dsp clock selection the default dsp clock is the internal 61.44 mhz generated by the pll. for test purpose, a different frequency may be provided via dsp_clk input pin. the selection between the internal 61.44 mhz or external clock source is done by the dsp_frq input pin. 4.12.3 pcm master/slave mode clocks selection in pcm master mode, the pfs and pdc are derived from the internal 16.384 mhz signal, and driven to the pcm interface via the pfs pin (output) and pdc pin (output). in pcm slave mode, the pfs and pdc are generated from an external signal, and input to the delic via the pfs pin and the pdc pin. note: during reset, a strap pin determines whether the delic operates in clock master or slave mode. 4.12.4 delic clock system synchronization the pcm clock division chain is synchronized to an external reference clock, used as one of the inputs to a phase comparator, after being divided into 8 khz. the other phase comparator input is the 8 khz clock, derived from the 16.384 mhz clock. the phase comparator output is used as control input of the dcxo, after being filtered by a low-pass filter. the reference clock can be driven by one of the following input pins: xclk - 2.048 mhz, 1.536 mhz or 8 khz: can be driven by a layer-1 transceiver (e.g. vip, quat-s) connected to the central office. only a clock master delic can be synchronized directly according to this input. in other cases (clock slave delic), this input signal may be divided to 8 khz or 512 khz, and driven out via refclk, in purpose to be used for the synchronization of the clock-master delic. refclk - 512 khz or 8 khz: used for synchronization of the clock master delic, when not synchronized by xclk. usually this signal is driven by a clock slave delic, or another pbx in the system. in a clock slave delic this pin is used as output. pfs - 8 khz: driven by the system clock master. may be used for synchronization of the clock slave delics. in a clock master delic this pin is used as output. 4.12.5 iom-2 clock selection the iom-2 interface clocks fsc and dcl are always output. the fsc output signal is usually generated with 50% duty cycle. a short fsc pulse is required for multiframe start indication (one dcl cycle long). one cycle after the short fsc pulse, the normal fsc is generated again with 50% duty cycle.
delic peb 20571 functional description preliminary data sheet 4-53 2003-08 4.12.6 iom-2000 clock selection the iom-2000 interface uses the same fsc like iom-2, whereas the data clock dcl2000 is a dedicated pin (always output). 4.12.7 refclk configuration refclk is an i/o pin for synchronizing the pcm interface (to 8 khz or 512 khz). the clock master delic may synchronize the internal clocks to refclk by selecting refclk as the reference clock source. a clock slave delic may use refclk as output, when refclk is driven by the xclk input pin. the slave delic may transfer the xclk signal to the clock master delic, and enable the clock master to synchronize to a layer-1 device, which is connected to another delic in the system. 4.12.8 ghdlc clock selection any of the next signals may be provided to the ghdlc channel as input clock: 1. lclk input pin this option is possible only when a lnc interface is assigned to the ghdlc unit. 2. 2.048 mhz, 4.096 mhz, or 8.192 mhz these clock signals are generated internally by the pcm clocking path. the selected internal clock is also driven outward via lclk. note that one of these signals must be selected as the clock of the ghdlc channel when the delic is the clock master of this channel.
delic delic memory structure preliminary data sheet 5-1 2003-08 5 delic memory structure the following tables provide the delic memory map for the dsp and the p. 5.1 dsp address space 5.1.1 dsp register address space t 5.1.2 dsp program address space table 5-1 dsp registers address space address description d000 - d01f dcu registers d020 - d03f a/-law registers d040 - d05f iomu registers d060 - d07f pcmu registers d080 - d09f clocks registers d0a0 - d0bf transiu registers d0c0 - d0df ghdlc registers d100 - d17f p mailbox and dma mailbox registers d180 - d1ff hdlcu registers d1a0 - dfff not used table 5-2 dsp program address space address size description 0000 - 0fff 4kw program ram 1000 - f7ff 58kw not used f800 - ffff 2kw program rom
delic delic memory structure preliminary data sheet 5-2 2003-08 5.1.3 dsp data address space a1 table 5-3 occupied dsp data address space address size description 0000 - 03ff 1kw internal xram 2000 - 203f 64w ghdlc data buffer 2040 - 207f 64w reserved for testt (**) 4000 - 401f 32w hdlcu receive output buffer 4020 - 403f 32w hdlcu transmit input buffer 4040 - 405f 32w hdlcu command ram 4060 - 407f 32w hdlcu receive input buffer 4080 - 409f 32w hdlcu transmit output buffer 40a0 - 40bf 32w hdlcu status buffer 6000 - 605f 96w transiu receive data buffer 6080 - 60df 96w transiu transmit data buffer 6100 - 61bf 192w reserved for test (**) 6200 - 6248 72w reserved for test (**) 6280 - 62c8 72w reserved for test (**) 8000 - 803f 64w iomu receive data buffer 8040 - 807f 64w iomu transmit data buffer 8080 - 80ff 128w reserved for test (**) 9000 - 9017 24w hram for u pn scrambler 9020 - 9037 24w hram for u pn descrambler a000 - a07f 128w pcmu receive data buffer a080 - a0ff 128w pcmu transmit data buffer a100 - a1ff 256w reserved for testt (**) d000 - dfff 4kw oak memory mapped registers(*) e000 - e1ff 0.5kw a/ -law rom f400 - f7ee 1kw-16w emulation mail box (on scdi) f7f0 - f7ff 16w ocem ? registers fc00 - ffff 1kw internal yram
delic delic memory structure preliminary data sheet 5-3 2003-08 note: (*) the oak memory mapped registers address space is described in the following table: (**) accessing these addresses may cause unpredictable results table 5-4 oak memory mapped registers address space 5.2 p address space the p address space consists of the general mail-box registers, the dma mail-box registers (only in non-dma mode), the p-int erface control register, and the p-interface status register (misr) . address description d000 - d01f dcu registers d020 - d03f a/m-law registers d040 - d05f iomu registers d060 - d07f pcmu registers d080 - d09f clocks registers d0a0 - d0bf transiu registers d0c0 - d0df hdlcu registers d100 - d17f cpu+dma mailbox registers d180 - d1ff ghdlc registers d1a0 - dfff not used table 5-5 p address space table address description 00 h - 43 h 60 h - 62 h p- mail box registers 48 h , 68 h , 6a h p-configuration registers 6b h - 7f h reserved. accessing these addresses may cause unpredictable results
delic register description preliminary data sheet 6-1 2003-08 6 register description 6.1 register map table 6-1 transiu register map reg name access address reset value comment page no. ticr rd/wr d0a0 h 0000 h iom-2000 global configuration 6-10 tccr0 rd/wr d0a1 h ffff h channel 7..0 configuration 6-11 tccr1 rd/wr d0a2 h ffff h channel 15..8 configuration 6-11 tccr2 rd/wr d0a3 h ffff h channel 23..16 configuration 6-11 vipcmr0 wr d0a8 h 0000 h vip_0 command registers 6-12 vipcmr1 wr d0a9 h 0000 h vip_1 command registers 6-12 vipcmr2 wr d0aa h 0000 h vip_2 command registers 6-12 vipstr0 rd d0ac 0000 h vip_0 status register 6-14 vipstr1 rd d0ad h 0000 h vip_1 status register 6-14 vipstr2 rd d0ae h 0000 h vip_2 status register 6-14 ticcmr wr d0b0 h (ls-word) d0b1 h (ms-word) 0000 h 0000 h channel initialization command 6-15 ticstr rd d0b2 h (ls-word) d0b3 h (ms-word) 0000 h 0000 h channel initialization status 6-20 table 6-2 scrambler register map reg name access address reset value comment page no. scmod rd/wr d010 h 0003 h scrambler mode 6-21 scsta rd/wr d011 h undef. scrambler status 6-21
delic register description preliminary data sheet 6-2 2003-08 table 6-3 iomu register map reg name access address reset value comment page no. icr r/w d040 h 0002 h iomu control 6-22 isr r d041 h undef. iomu status 6-23 itscr set (w) d042 h 0000 h iomu tri-state control 6-24 reset (w) d043 h rd044 h idrdyr r d045 h undef. iomu drdy 6-25 idpr r/w d046 h 00e0 h iomu data prefix 6-26 table 6-4 pcmu register map reg name access address reset value comment page no. pcr rd/wr d060 h 00 h pcmu control 6-27 psr rd d061 h undef. pcmu status 6-28 ptsc0 rd/wr d062 h (read/set) d063 h (read/reset) 00 h pcmu tristate control 0 6-29 ptsc1 rd/wr d064 h (read/set) d065 h (read/reset) 00 h pcmu tristate control 1 6-29 ptsc2 rd/wr d066 h (read/set) d067 h (read/reset) 00 h pcmu tristate control 2 6-29 ptsc3 rd/wr d068 h (read/set) d069 h (read/reset) 00 h pcmu tristate control 3 6-29
delic register description preliminary data sheet 6-3 2003-08 . ptsc4 rd/wr d06a h (read/set) d06b h (read/reset) 00 h pcmu tristate control 4 6-29 ptsc5 rd/wr d06c h (read/set) d06d h (read/reset) 00 h pcmu tristate control 5 6-29 ptsc6 rd/wr d06e h (read/set) d06f h (read/reset) 00 h pcmu tristate control 6 6-29 ptsc7 rd/wr d070 h (read/set) d071 h (read/reset) 00 h pcmu tristate control 7 6-29 pdpr rd/wr d072 h e0 h pcmu data prefix 6-30 table 6-5 a-/-law unit register map reg name access address reset value comment page no. amcr r/w d020 h 00 h a/-law unit control 6-31 amir w d021 h undefin ed a/-law unit input 6-31 amor r d022 h undefin ed a/-law output 6-32 table 6-6 hdlcu register map reg name access address reset value comment page no. hcr w d180 h 0001 h hdlc control 6-33 hsta r d180 h 0001 h hdlc status 6-34 table 6-4 pcmu register map (continued) reg name access address reset value comment page no.
delic register description preliminary data sheet 6-4 2003-08 hccv r/w 4040 h -405f h undefin ed channel command vector 6-35 hcsv r 40a0 h -40bf h undefin ed channel status vector 6-36 table 6-7 ghdlc register map reg name access address reset value comment page no. gtest w d0c0 h 0001 h ghdlc test/ normal mode 6-38 gchm w d0c1 h 0000 h ghdlc channel mode 6-38 gint r d0d4 h 0000 h ghdlc interrupt 6-39 gfint r/w d0d3 h 0000 h ghdlc frame interrupt 6-39 grsta0 r d0c2 h 001f h ghdlc receive status cha. 0 6-40 grsta1 r d0c3 h 001f h ghdlc receive status cha. 1 6-40 grsta2 r d0c4 h 001f h ghdlc receive status cha. 2 6-40 grsta3 r d0c5 h 001f h ghdlc receive status cha. 3 6-40 rxdat rd 2000 h - 203f h 0000 h receive data and status 6-41 gmod0 w d0c6 h 0140 h ghdlc mode cha. 0 6-42 gmod1 w d0c7 h 0140 h ghdlc mode cha. 1 6-42 gmod2 w d0c8 h 0140 h ghdlc mode cha. 2 6-42 gmod3 w d0c9 h 0140 h ghdlc mode cha. 3 6-42 gtcmd0 w d0ca h 0000 h ghdlc tx command cha. 0 6-43 gtcmd1 w d0cc h 0000 h ghdlc tx command cha. 1 6-43 gtcmd2 w d0ce h 0000 h ghdlc tx command cha. 2 6-43 gtcmd3 w d0d0 h 0000 h ghdlc tx command cha. 3 6-43 gasync r/w d0d2 h 0000 h async control/ status 6-44 glclk0 r/w d08a h 0000 h lclk0 control register 6-45 glclk1 r/w d08b h 0000 h lclk1 control register 6-46 glclk2 r/w d08c h 0000 h lclk2 control register 6-47 table 6-6 hdlcu register map (continued) reg name access address reset value comment page no.
delic register description preliminary data sheet 6-5 2003-08 glclk3 r/w d08d h 0000 h lclk3 control register 6-48 muxctrl r/w d14a h 0000 h multiplexer control 6-49 table 6-8 dcu register map reg name access address reset value comment page no. imask r/w d002 h 0000 h interrupt mask 6-50 steve r d003 h 0000 h status event 6-50 statc r d004 h unchan. statistics counter 6-51 stati r d005 h 0000 h statistics 6-52 table 6-9 p configuration register map regist. (16 bit) des- cription reset value bit dsp word access p byte access p- addr. msb of word p- addr. lsb of word dsp addr. page no. mcfg configur ation 0 h 6 r r/w none 48 h d148 h 6-52 vdev device version hardwired 8 none r none 6a h none 6-54 ivec int vector reg un- changed 8 r/w r none 68 h d168 h 6-54 table 6-7 ghdlc register map (continued) reg name access address reset value comment page no.
delic register description preliminary data sheet 6-6 2003-08 table 6-10 general mailbox register map register (16 bit) descrip- tion reset value bit dsp word access p byte acc. p- addr. msb of word p- addr. lsb of word dsp addr. page no. mcmd p command 00 h 8r w none 40 h d140 h 6-55 mbusy p mb busy 0 h 1w r 41 h none d141 h 6-55 mgen p generic data reg. unchanged 16 r w 43 h 42 h d142 h (lsb) d143 h (msb) d144 h (all) 6-56 mdt0 p data reg0 unchanged 16 r w 01 h 00 h d100 h 6-57 mdt1 p data reg1 unchanged 16 r w 03 h 02 h d102 h 6-57 mdt2 p data reg2 unchanged 16 r w 05 h 04 h d104 h 6-57 mdt3 p data reg3 unchanged 16 r w 07 h 06 h d106 h 6-57 mdt4 p data reg4 unchanged 16 r w 09 h 08 h d108 h 6-57 mdt5 p data reg5 unchanged 16 r w 0b h 0a h d10a h 6-57 mdt6 p data reg6 unchanged 16 r w 0d h 0c h d10c h 6-57 mdt7 p data reg7 unchanged 16 r w 0f h 0e h d10e h 6-57 ocmd dsp command 00 h 8w r none 60 h d160 h 6-57 obusy dsp mb busy 0 h 1r r/w61 h none d161 h 6-58 ogen dsp generic data reg unchanged 16 w r 63 h 62 h d162 h (lsb) d163 h (msb) d164 h (all) 6-59 odt0 dsp data reg0 unchanged 16 w r 21 h 20 h d120 h 6-59
delic register description preliminary data sheet 6-7 2003-08 note: mdt8..15 and odt8..15 are accessible only in non-dma mode, when the dma mailbox data registers are used for doubling the size of general mailbox. odt1 dsp data reg1 unchanged 16 w r 23 h 22 h d122 h 6-59 odt2 dsp data reg2 unchanged 16 w r 25 h 24 h d124 h 6-59 odt3 dsp data reg3 unchanged 16 w r 27 h 26 h d126 h 6-59 odt4 dsp data reg4 unchanged 16 w r 29 h 28 h d128 h 6-59 odt5 dsp data reg5 unchanged 16 w r 2b h 2a h d12a h 6-59 odt6 dsp data reg6 unchanged 16 w r 2d h 2c h d12c h 6-59 odt7 dsp data reg7 unchanged 16 w r 2f h 2e h d12e h 6-59 table 6-11 dma mailbox register map register description reset value bit dsp access dma / p acc. p msb addr. p lsb addr. dsp addr. page no. dtxcnt tx counter 0 h 4 r/w none none none d150 h 6-60 dinsta dma int status 0 h 4 r none none none d152 h 6-61 tdt0/ mdt8 tx data reg0/ p data reg8 un- changed 16 r w 11 h 10 h d110 h 6-57 tdt1/ mdt9 tx data reg1/ p data reg9 un- changed 16 r w 13 h 12 h d112 h 6-57 tdt2/ mdt10 tx data reg2/ p data reg10 un- changed 16 r w 15 h 14 h d114 h 6-57 table 6-10 general mailbox register map (continued) register (16 bit) descrip- tion reset value bit dsp word access p byte acc. p- addr. msb of word p- addr. lsb of word dsp addr. page no.
delic register description preliminary data sheet 6-8 2003-08 tdt3/ mdt11 tx data reg3/ p data reg11 un- changed 16 r w 17 h 16 h d116 h 6-57 tdt4/ mdt12 tx data reg4/ p data reg12 un- changed 16 r w 19 h 18 h d118 h 6-57 tdt5/ mdt13 tx data reg5/ p data reg13 un- changed 16 r w 1b h 1a h d11a h 6-57 tdt6/ mdt14 tx data reg6/ p data reg14 un- changed 16 r w 1d h 1c h d11c h 6-57 tdt7/ mdt15 tx data reg7/ p data reg15 un- changed 16 r w 1f h 1e h d11e h 6-57 drxcnt rx counter 0 h 4 r/w none none none d170 h 6-60 rdt0/ odt8 rx data reg0/ dsp data reg8 un- changed 16 w r 31 h 30 h d130 h 6-59 rdt1/ odt9 rx data reg1/ dsp data reg9 un- changed 16 w r 33 h 32 h d132 h 6-59 rdt2/ odt10 rx data reg2/ dsp data reg10 un- changed 16 w r 35 h 34 h d134 h 6-59 rdt3/ odt11 rx data reg3/ dsp data reg11 un- changed 16 w r 37 h 36 h d136 h 6-59 rdt4/ odt12 rx data reg4/ dsp data reg12 un- changed 16 w r 39 h 38 h d138 h 6-59 rdt5/ odt13 rx data reg5/ dsp data reg13 un- changed 16 w r 3b h 3a h d13a h 6-59 rdt6/ odt14 rx data reg6/ dsp data reg14 un- changed 16 w r 3d h 3c h d13c h 6-59 rdt7/ odt15 rx data reg7/ dsp data reg15 un- changed 16 w r 3f h 3e h d13e h 6-59 table 6-11 dma mailbox register map (continued) register description reset value bit dsp access dma / p acc. p msb addr. p lsb addr. dsp addr. page no.
delic register description preliminary data sheet 6-9 2003-08 note: mdt8..15 and odt8..15 are accessible only in non-dma mode, when the dma mailbox data registers are used for doubling the size of general mailbox. .. table 6-12 clock generator register map reg name access address reset value comment page no. cpdc r/w d080 h 0000 h pdc control 6-62 cpfs r/w d081 h 0001 h pfs control 6-62 clkout r/w d082 h 0008 h clkout control 6-63 crefsel r/w d083 h 0000 h dcxo reference clock selection 6-64 crefclk r/w d084 h 0003 h refclk control 6-65 cdcl2 r/w d085 h 0004 h dcl_2000 control 6-65 cdcl r/w d086 h 000b h dcl control 6-66 cfsc r/w d087 h 0002 h fsc control 6-67 cl1clk r/w d088 h 0000 h l1_clk control 6-68 cpfssy r/w d089 h 0000 h pfs synchronization mode 6-69 crtcnt r d08e h 0000 h real-time counter 6-69 cstrap r/w d08f h xxxx xxxx xxxx xx10 b strap status register 6-70
delic register description preliminary data sheet 6-10 2003-08 6.2 detailed register description 6.2.1 transiu register description 6.2.1.1 transiu iom-2000 configuration register ticr register read/write address: d0a0 h reset value: 0000 h note: the reset value of bit 4kfsc is undefined, since this read-only bit is toggled every 250 s. 15 14 13 12 11 10 9 8 xxxxxxxx 76543210 x x x 4kfsc cmden dxen dr1 dr0 dr1..0 iom-2000 data rate and channel number 00 = 3.072 mbit/s data rate; 8 iom-2000 channels are supported 01 = 6.144 mbit/s data rate; 16 iom-2000 channels are supported 10 = 12.288 mbit/s data rate; 24 iom-2000 channels are supported 11 = reserved dxen dx line enable 0 = iom-2000 dx line to the vip is in tri-state 1 = iom-2000 dx line to the vip is enabled (starting with the next 4 khz frame) cmden cmd line enable 0 = iom-2000 cmd line to the vip is in tri-state 1 = iom-2000 cmd line to the vip is enabled 4kfsc 4 khz fsc (read only) 0 = in the transiu, the current 8 khz iom-2000 frame starts in the second half of the current 4 khz upn of s/t frame 1 = in the transiu, the current 8 khz iom-2000 frame starts in the first half of the current 4 khz upn of s/t frame
delic register description preliminary data sheet 6-11 2003-08 note: ?x? = unused (read as ?0?) 6.2.1.2 transiu channel configuration registers the channel registers are used for iom-2000 channel disabling and mode programming. each iom-2000 channel may be programmed to upn, lt-s, or lt-t mode, or completely disabled. important only four channels out of eight channels are programmable to upn and s/t modes in vip peb 20590, the remaining four channels may be operated as upn transceiver only. it is the user?s responsiblity to ensure that the iom-2000 channels in the transiu are correctly configurated in order to match with the line configuration of the vip (see below: registers tccr0 - 3 read/write address: tccr0: d0a1 h tccr1: d0a2 h tccr2: d0a3 h reset values: ffff h table 6-13 available isdn modes for each vip channel vip_0,1,2 channel 01234567 transiu channel 0 8 16 1 9 17 2 10 18 3 11 19 4 12 20 5 13 21 6 14 22 7 15 23 available vip mode upn upn s/t upn upn s/t upn upn s/t upn upn s/t available vip8 mode upn s/t upn s/t upn s/t upn s/t upn s/t upn s/t upn s/t upn s/t 15 14 13 12 11 10 9 8 c7m(1:0) c6m(1:0) c5m(1:0) c4m(1:0) 76543210 c3m(1:0) c2m(1:0) c1m(1:0) c0m(1:0)
delic register description preliminary data sheet 6-12 2003-08 note: tccr0 (channel 7..0), tccr1 (channel 15..8) and tccr2 (channel 23..16) have the same structure, only tcrr1 is shown here. 6.2.1.3 vip command registers (vipcmr0, vipcmr1, vipcmr2) the vipcmr0-2 registers contain command information dedicated to the vip 0, 1, 2 (only the vipcmr0 is shown here, vipcmr1 and vipcmr2 have the same structure). vipcmr register write address: vipcmr0: d0a8 h vipcmr1: d0a9 h vipcmr2 h : d0aa h reset value: 0000 h c7..0m(1:0) operational mode of iom-2000 channel7..0 00 = channel is configured to s mode (lt-s) 01 = channel is configured to s mode (lt-t) 10 = channel is configured to upn mode 11 = channel is disabled, ?0?s are sent on the dx line 15 14 13 12 11 10 9 8 xxxxrd_npllppssh_fscdelre 76543210 delch(2:0) exref refsel (2:0) wr_n wr_n write command to vip_n (s/t, u pn ) 0 = data sent to vip_n is invalid 1 = data sent to vip_n is valid refsel(2:0) reference clock channel select (lt-t)
delic register description preliminary data sheet 6-13 2003-08 the reference clock signal for the delic oscillator is generated from the internal vip_n channel_m coded in these 3 bits and passed on via pin refclk to the next cascaded vip or directly to the delic 000 = reference clock provided by channel_0 001 = reference clock provided by channel_1 ... 007 = reference clock provided by channel_7 exref external reference clock selection (lt-t) 0 = no external reference clock source. reference clock is generated from internal vip_n channel specified in refclk(2:0) and passed on via refclk pin to vip_n-1 or directly to delic. 1 = reference clock is generated from external source via pin inclk and passed on via refclk pin to vip_n-1 or directly to delic. the internal reference clock generation logic is disabled. note that vip_0 has the highest priority in terms of clock selection delch(2:0) delay measurement channel selection (u pn ) selects one of the eight upn line interface channels of each vip where the delay is to be measured. 000 = delay is measured in upn channel_0 001 = delay is measured in upn channel_1 ... 111 = delay is measured in upn channel_7 delre delay counter resolution (u pn ) resolution of the delay counter. 0 = resolution of 65 ns (15.36 mhz period) 1 = resolution of 130 ns (7.68 mhz period) note: using a resolution of 65 ns, the maximum delay of 20.8 s is not covered (refer to delay(7:0) bits) sh_fsc short fsc pulse 0 = the next fsc frame is no superframe 1 = the next fsc is assumed as superframe pllpps pll positive pulse sensing
delic register description preliminary data sheet 6-14 2003-08 note: unused bits (x) read as ?0?. the registers are reset upon every 8 khz frame sync to avoid multiple data transmit/receive to/from the vip. 6.2.1.4 vip status registers the vipstr0-2 registers contain the status bits received from the dedicated vip for vips 0, 1, 2 respectively (all three registers have the same structure). vipstr register read address: vipstr0: d0ac h , vipstr1: d0ad h , vipstr2: d0ae h reset value: 0000 h 0 = normal operation 1 = the clock recovering plls of all vip channels operate on positive line pulses only rd_n read request to vip status register s_n (s/t, u pn ) 0 = no register read 1 = the dsp reads the vip register (during initialization, debugging or error conditions). the register value is available for the read operation in the consecutive frame (after the next fsc). note: to avoid blocking, the dsp must not issue this bit during normal operation. 15 14 13 12 11 10 9 8 xxxxxxxx 76543210 delay(7:0)
delic register description preliminary data sheet 6-15 2003-08 note: unused bits (x) read as ?0?. 6.2.1.5 transiu initialization channel command register the initialization channel command register contains the command bits for vip_n, channel_m together with 5 bits of the vip channel address. the vip only acts upon the command bits if they were declared valid by the delic issuing a write command. bit wr is dedicated to the command bits of groups conf1, conf2 and tst2, whereas wr_st informs the vip about changes in the layer 1 state machine of the delic (smini(2:0) and msync bits). the delic may also explicitly read the vip?s status information by issueing bit rd. the reset value of each bit is ?0? except bits mode(2:0) which are set to ?011? note: a read command to the vip must not be issued during normal operation to avoid a loss of information when the vip is reporting status information at the same time. delay(7:0) line delay value (u pn ) returns the value of the measured line delay (in s) between the upn transmit and receive frame with a resolution of 65 ns or 130 ns (programmable in vipcmr.delre bits). the value indicates the delay between the transmitted m-bit and the received lf-bit (minus the u pn guard time of 2 bits). the delay for one direction equals to the measured delay divided by two. the channel address for the delay measurement is coded in vipcmr.delch(2:0) bits. the vip provides 2 values in one u pn frame (one every 125 s) from which the bigger one is the valid. note: the transceiver delays of the vip are included in the delay measurement.
delic register description preliminary data sheet 6-16 2003-08 ticcmr register write address: ls-word: d0b0 h , ms-word: d0b1 h reset value: 0000 h 31 30 29 28 27 26 25 24 x vipadr(1:0) chadr(2:0) fil exlp 23 22 21 20 19 18 17 16 plls pd dhen x x pdown loop tx_en 15 14 13 12 11 10 9 8 pllint aac(1:0) bbc(1:0) owin(2:0) 76543210 mf_en mode(2:0) mosel(1:0) rd wr wr write command (s/t, u pn ) 0 = data sent in these bits is invalid 1 = all configuration bits contain valid data note: does not apply to smini(2:0) and msync bits rd read request to vip command bits (s/t, u pn ) 0 = normal operation 1 = delic read request of the ticcmr register which was sent to the vip. it includes initialization and configuration commands and the channel addresses. the vip returns these values (instead of sending the actual vip status information) within the iom-2000 stat_n_m bit stream. the values are available in the next frame (after next fsc) in delic ticstr register. note: to avoid blocking, the delic must not issue this bit during normal operation . mosel(1:0) interface mode selection (s/t, u pn ) 00 = channel programmed to s/t mode 01 = channel programmed to u pn mode 10 = reserved
delic register description preliminary data sheet 6-17 2003-08 11 = reserved mode(2:0) mode configuration (s/t, u pn ) 001 = channel programmed to lt-t mode 011 = channel programmed to lt-s mode (point-to-point or extended passive bus configuration) or u pn mode 111 = channel programmed to lt-s mode (short passive bus mode) note: all other states are reserved. the reset value is 011, e.g. the default mode of vip is lt-s mf_en multiframe enable (s/t) 0 = multiframes are disabled 1 = multiframes are enabled owin(2:0) oversampling window size (s/t, u pn ) specifies the width of the oversampling window in bit samples. the window is centered about the middle of the bit. for example, a size of 16 means that, upon detection of (16/2) = 8 times logical ?1?, the received bit is detected as ?1?. the window size is programmed in steps of two as shown below: 000 = 2 001 = 4 010 = 6 ... 111 = 16 bbc(1:0) balancing bit control (u pn ) 0x = adaptive generation of balancing bit (depending on line delay). upon reception of info3 or info4 10 = balancing bit control is disabled, and no balancing bit is added 11 = balancing bit control is disabled, and balancing bit is added after each code violation in the m-bit (info3 or info4) aac(1:0) adaptive amplifier control (s/t, u pn ) 0x = adaptive amplifier control in vip is enabled. the amplifier and the equalizer are switched on/off depending on the level of the received line signal with respect to the comparator threshold. 10 = adaptive amplifier control is disabled. the amplifier and the equalizer are switched off permanently.
delic register description preliminary data sheet 6-18 2003-08 11 = adaptive amplifier control is disabled. the amplifier and the equalizer are switched on permanently pllint receive pll integrator (u pn ) 0 = programmable deviation disabled 1 = programmable deviation enabled, i.e., the rxpll reacts only after a certain number of consequent deviations from the pll controlling range. tx_en transmitter enable (s/t, u pn ) 0 = transmitter (analog line driver) is disabled (e.g. for non- transparent analog loops in lt-t) 1 = transmitter is enabled (e.g. for switching of transparent analog loops in lt-s) loop loop-back mode in vip enable (s/t, u pn ) 0 = loops disabled 1 = loop-back enabled. channel_m transmit data is looped back to the receive data path (either transparent or non-transparent according to state of bit tx_en). depending on bit exlp the loop is closed internally or externally. pdown power down mode (s/t, u pn ) 0 = operational mode 1 = channel_m in power-down mode (only the level detector in the vip receiver is in operational mode) dhen d-channel handling enable (lt-t) 0 = d-channel transmitted transparently, without any condition 1 = d-channel transmitted transparently if no collision is detected (e=d), if collision is detected (e d) ?1s? are transmitted in d- channel pd phase deviation selection (lt-t) 0 = phase deviation = (2 bits - 2 oscillator periods + analog delay) 1 = phase deviation = (2 bits - 4 oscillator periods + analog delay) plls receive pll adjustment (s/t, u pn ) 0 = tracking step equals 0.5 oscillator period 1 = tracking step equals 1.0 oscillator period exlp external loop (s/t, u pn )
delic register description preliminary data sheet 6-19 2003-08 note: unused bits (x) read as ?0?. 0 = no external analog loop. if bit loop=1 the loop is closed internally 1 = external analog loop. if bit loop=1 the loop is closed externally fil filter enable (u pn only) 0 = filter of equalizer inside the vip receiver disabled 1 = filter of equalizer inside the vip receiver enabled chadr(2:0) channel_m address for commands 000 = command word is dedicated to vip_n channel_0 001 = command word is dedicated to vip_n channel_1 010 = command word is dedicated to vip_n channel_2 011 = command word is dedicated to vip_n channel_3 100 = command word is dedicated to vip_n channel_4 101 = command word is dedicated to vip_n channel_5 110 = command word is dedicated to vip_n channel_6 111 = command word is dedicated to vip_n channel_7 vipadr(2:0) vip_n address for commands 00 = command word is dedicated to vip_0 01 = command word is dedicated to vip_1 10 = command word is dedicated to vip_2 11 = reserved
delic register description preliminary data sheet 6-20 2003-08 6.2.1.6 transiu initialization channel status register (ticstr) the initialization channel status register contains the command bits to vip_n, channel_m mirrored by the vip in response to a read command issued by the delic in the previous frame. note: the actual status information from the vip channels is stored in the data ram to make it accessible for the delic layer-1 state machine software in the dsp. ticstr register read address: ls-word: d0b2 h , ms-word: d0b3 h reset value: 0000 h 31 30 29 28 27 26 25 24 x vipadr(1:0) chadr(2:0) fil exlp 23 22 21 20 19 18 17 16 plls pd dhen x x pdown loop tx_en 15 14 13 12 11 10 9 8 pllint aac(1:0) bbc(1:0) owin(2:0) 76543210 mf_en mode(2:0) mosel(1:0) rd wr
delic register description preliminary data sheet 6-21 2003-08 6.2.1.7 scrambler mode register scmod register read/write address: d010 h reset value: 0003 h 6.2.1.8 scrambler status register scsta register read/write address: d011 h reset value: undefined 15 14 13 12 11 10 9 8 xxxxxxxx 76543210 xxxxxxscmod1..0 scmod1..0 scrambling mode of the upn line interface 00 = scrambling according to itu-t v.27 01 = scrambling compatible to octat-p peb 2096 10 = reserved 11 = no scrambling 15 14 13 12 11 10 9 8 xxxxxxxx 76543210 xxxxxxxscsta scsta scrambler status 0 = write access: start of scrambling algorithm for all channels enabled in the hram read access: scrambler is processing data
delic register description preliminary data sheet 6-22 2003-08 note: both values ?0? or ?1? written to scsta will start the scrambling 6.2.2 iomu register description 6.2.2.1 iomu control register icr register read/write address: d040 h reset value: 02 h 1 = write access: start of scrambling algorithm for all channels enabled in the hram read access: scrambling has finished 15 14 13 12 11 10 9 8 xxxxxxxx 76543210 x x icdb a od dc dr(1:0) icdb idle current d-buffer ( for test purpose; only if iomu is in idle mode: icr:a = ?0?) 0 = make frame buffer 0 accessible to the dsp 1 = make frame buffer 1 accessible to the dsp a iomu activation 0 = the iomu is idle. the state machine of the iomu is idle, and no accesses to the i-buffer are executed by the iomu. 1 = the iomu is active, and works according to the programming of the other control register bits. od dd0 and dd1 output mode 0 = push-pull mode. 1 = open-drain mode dc double data rate clock 0 = single clock (dcl frequency is identical to the iom-2 data rate)
delic register description preliminary data sheet 6-23 2003-08 6.2.2.2 iomu status register isr register read/write address: d041 h reset value: undefined note: (x) unused bits read as ?0? 1 = double clock (dcl frequency is double the iom-2 data rate) dr(1:0) iom-2 data rate 00 = iom-2 data rate of 1 x 384 kbit/s (1 x 6 time slots/frame) 01 = iom-2 data rate of 1 x 768 kbit/s (1 x 12 time slots/frame) 10 = iom-2 data rate of 2 x 2.048 mbit/s (2 x 32 time slots/frame) (default) 11 = iom-2 data rate of 1 x 4.096 mbit/s (1 x 64 time slots/frame) 15 14 13 12 11 10 9 8 ibuffxxxxxxx 76543210 xxxxxxxx ibuff i-buffer index note: used for testing. may also be used in double data rate mode of the iomu to determine if the iomu buffers have been swapped already 0 = buffer 0 is currently used as i-buffer, buffer 1 is used as d-buffer 1 = buffer 1 is currently used as i-buffer, buffer 0 is used as d-buffer
delic register description preliminary data sheet 6-24 2003-08 6.2.2.3 iomu tri-state control register itscr register read/write address: set address: d042 h reset address: d043 h read address: d044 h reset value: 00 h 15 14 13 12 11 10 9 8 ts(15:8) 76543210 ts(7:0) ts(15:0) every bit determines whether dd0/1 output is in tri-state during the time slot sequence. the time slot sequence length, indices and port controlled by each ts-bit is defined according the iomu data rate mode (icr.dr(1:0)) 0 = dd0/1 is in tri-state during the related time slot sequence 1 = dd0/1 is driven by the iomu during the related time slot sequence table 6-14 tristate control assi gnment for iom-2 time slots itscr bit 1 x 6 ts/frame 1 x 12 ts/frame 2 x 32 ts/frame 1 x 64 ts/frame dd0 ts dd0 ts dd0/1 ts dd0/1 ts ts0 dd0 0 dd0 0 dd0 0-3 dd0 0-3 ts1 dd0 1 dd0 1 dd0 4-7 dd0 4-7 ts2 dd0 2 dd0 2 dd0 8-11 dd0 8-11 ts3 dd0 3 dd0 3 dd0 12-15 dd0 12-15 ts4 dd0 4 dd0 4 dd0 16-19 dd0 16-19 ts5 dd0 5 dd0 5 dd0 20-23 dd0 20-23 ts6 not used dd0 6 dd0 24-27 dd0 24-27 ts7 not used dd0 7 dd0 28-31 dd0 28-31 ts8 not used dd0 8 dd1 0-3 dd0 32-35
delic register description preliminary data sheet 6-25 2003-08 6.2.2.4 iomu drdy register idrdyr register read address: d045 h reset value: undefined ts9 not used dd0 9 dd1 4-7 dd0 36-39 ts10 not used dd0 10 dd1 8-11 dd0 40-43 ts11 not used dd0 11 dd1 12-15 dd0 44-47 ts12 not used not used dd1 16-19 dd0 48-51 ts13 not used not used dd1 20-23 dd0 52-55 ts14 not used not used dd1 24-27 dd0 56-59 ts15 not used not used dd1 28-31 dd0 60-63 15 14 13 12 11 10 9 8 00000000 76543210 ds(7:0) bit drdy sample dsx indicates the availability of the d-channels of the previous frame. 0 = stop (d-channel blocked due to collision), 1 = go e.g. ds1 was sampled during the d-channel of iom-2 channel 1, etc. ds0 corresponds to d-channel of iom-2 port 0 cha 0 ds1 corresponds to d-channel of iom-2 port 0 cha 1 ds2 corresponds to d-channel of iom-2 port 0 cha 2 ds3 corresponds to d-channel of iom-2 port 0 cha 3 ds4 corresponds to d-channel of iom-2 port 0 cha 4 ds5 corresponds to d-channel of iom-2 port 0 cha 5 ds6 corresponds to d-channel of iom-2 port 0 cha 6 ds7 corresponds to d-channel of iom-2 port 0 cha 7 table 6-14 tristate control assignme nt for iom-2 time slots (continued) itscr bit 1 x 6 ts/frame 1 x 12 ts/frame 2 x 32 ts/frame 1 x 64 ts/frame dd0 ts dd0 ts dd0/1 ts dd0/1 ts
delic register description preliminary data sheet 6-26 2003-08 note: in 1 x 4.096 mbit/s mode (i.e.16 iom-2 channels/frame), drdy is sampled only during the d-channels of the first eight iom-2 channels of every frame. 6.2.2.5 iomu data prefix register idpr register read/write address: d046 h reset value: e0 h note: (x) unused bits read as ?0? 15 14 13 12 11 10 9 8 idp(7:0) 76543210 xxxxxxxx idp(7:0) iomu data prefix determines the high byte of every word being read from the iom circular- buffer (i-buffer or d-buffer). the low byte is the data being read from the circular buffer. after reset this register contains the msb of the base address of the a-law- to-linear rom table: e0 h .
delic register description preliminary data sheet 6-27 2003-08 6.2.3 pcmu register description 6.2.3.1 pcmu command register pcr register read/write address: d060 h reset value: 0000 h 15 14 13 12 11 10 9 8 xxxxxxxx 76543210 x x sfh icdb pa pdcl pdr(1:0) pdr(1:0) pcm data rate 00 = 4 x 2.048 mbit/s (4 x 32 time slots per frame) 01 = 2 x 4.096 mbit/s (2 x 64 time slots per frame) 10 = 1 x 8.092 mbit/s (1 x 128 time slots per frame) 11 = 1 x 16.384 mbit/s (1 x 256 time slots per frame, if only first or second half of 8 khz frame is handled) pdcl pcm double data rate clock 0 = single data rate clock 1 = double data rate clock pa pcmu activation 0 = the pcmu is in idle mode 1 = the pcmu is in active mode icdb idle current d-buffer used only for testing of pcmu in idle mode (pcr:pa = '0') to determine which buffer is being accessed by the dsp 0 = frame buffer 0 is accessed by the dsp 1 = frame buffer 1 is accessed by the dsp sfh second frame half used only in 1 x 256 time slots per frame data rate mode 0 = the first 128 time slots of each frame are handled by the pcmu
delic register description preliminary data sheet 6-28 2003-08 note: ?x? = unused (read as ?0?) 6.2.3.2 pcmu status register psr register read/write address: d061 h reset value: undefined note: (x) unused bits read as ?0? 1 = the second 128 time slots of each frame are handled by the pcmu 15 14 13 12 11 10 9 8 pbuffxxxxxxx 76543210 xxxxxxxx pbuff p-buffer index note: used for testing. may also be used in double data rate mode of the pcmu to determine if the pcmu buffers have been swapped already 0 = buffer 0 is currently used as p-buffer, buffer 1 is used as d-buffer 1 = buffer 1 is currently used as p-buffer, buffer 0 is used as d-buffer
delic register description preliminary data sheet 6-29 2003-08 6.2.3.3 pcmu tri-state control registers ptsc0 register read/write read address: d062-63 h (set/reset) set address: d062 h reset address: d063 h ptsc1 register read/write read address: d064-65 h (set/reset) set address: d064 h reset address: d065 h ptsc2 register read/write read address: d066-67 h (set/reset) set address: d066 h reset address: d067 h ptsc3 register read/write read address: d068-69 h (set/reset) set address: d068 h reset address: d069 h ptsc4 register read/write read address: d06a-6b h (set/reset) set address: d06a h reset address: d06b h ptsc5 register read/write read address: d06c-6d h (set/reset) set address: d06c h reset address: d06d h ptsc6 register read/write read address: d06e-6f h (set/reset) set address: d06e h reset address: d06f h ptsc7 register read/write read address: d070-71 h (set/reset) set address: d070 h reset address: d071 h reset values (ptsc0..7): 0000 h 15 14 13 12 11 10 9 8 ptscn(15:8)
delic register description preliminary data sheet 6-30 2003-08 6.2.3.4 pcmu data prefix register pdpr register read/write address: d072 h reset value: e0 h note: (x) unused bits read as ?0? 76543210 ptscn(7:0) ptscn (15..0) tristate control for each pcm time slot 0 = the controlled time slot is invalid 1 = the controlled time slot is valid 15 14 13 12 11 10 9 8 pdp(7:0) 76543210 xxxxxxxx pdp(7:0) pcmu data prefix the data written to this register is read as the most significant byte of every time slot read by the dsp from the pcmu frame buffers. can be used for quick access to the a/-law rom, for conversion of compressed data (received via the pcm interface) into linear value. after reset this register contains the msb of the base address of the a-law- to-linear rom table: e0 h . to enable quick conversion from -law to linear, the pcmu data prefix register should be programmed to e1 h .
delic register description preliminary data sheet 6-31 2003-08 6.2.4 a-/-law unit register description 6.2.4.1 a/-law unit control register a/-law unit control register (amcr) read/write address: d020 h reset value: 0000 h note: ?x? = unused bits this register controls the conversion mode of the a/-law unit 6.2.4.2 a/-law input register a/-law unit input register (amir) write address: d021 h reset value: undefined note: - in -law mode, only the 14 msbs are processed. - in a-law mode, only the 13 msbs are processed. 15 14 13 12 11 10 9 8 xxxxxxxx 76543210 xxxxxxxmode mode a/-law mode programming 0 = conversion from linear value to a-law value (default) 1 = conversion from linear value to -law value 15 14 13 12 11 10 9 8 ind(15:8) 76543210 ind(7:0) ind(15:0) linear input data
delic register description preliminary data sheet 6-32 2003-08 6.2.4.3 a/-law output register a/-law unit output register (amor) read address: d022 h reset value: undefined note: ?x? = unused bits, driven to ?0? provides the linear input data that is to be converted into logarithmic data format according to a-law or -law algorithm. 15 14 13 12 11 10 9 8 xxxxxxxx 76543210 outd(7:0) outd(7:0) logarithmic output data provides the logarithmic output data generated by the a/--law unit out of the linear input data. the data format (a-law or -law) depends on the the selected conversion algorithm.
delic register description preliminary data sheet 6-33 2003-08 6.2.5 hdlcu registers description 6.2.5.1 hdlcu control register in order to enable dsp access all the buffers and rams, dspctrl bit must be set to ?1?. hcr register write address: d180 h reset value: 0001 h note: each time dspctrl is set, hprs is also set. 15 14 13 12 11 10 9 8 xxxxxxx x 7654321 0 x hprs(5:0) dspctrl hprs(5:0) hdlcu channel preset the number of hdlc channels to be processed by the hdlcu dspctrl dsp access control to the hdlcu 0 = the dsp must not access the hdlcu buffers and rams 1 = the dsp may access the hdlcu buffers
delic register description preliminary data sheet 6-34 2003-08 6.2.5.2 hdlcu status register hsta register read address: d180 h reset value: 0001 h 15 14 13 12 11 10 9 8 hhold bitor x chcnt(5:1) 76543210 chcnt(0) hprs(5:0) dspctrl dspctrl dsp access control to the hdlcu 0 = the hdlcu is currently processing the channel 1 = the dsp is currently accessing the hdlcu hprs(5:0) hdlc channel preset number of hdlc channels handled by the hdlcu (max. 32) chcnt(5:0) channel count number of channels that have already been processed in the current frame bitor bitorder determines the order of bits inside an hdlc data byte going to (coming from) the iomu, pcmu or transiu. 0 = hdlc data is transmitted with msb first 1 = hdlc data is transmitted with lsb first hhold hdlcu busy indicator 0 = hdlcu is processing the current frame 1 = hdlcu has finished processing the current frame
delic register description preliminary data sheet 6-35 2003-08 6.2.5.3 channel command vector hccv registers read/ write addresses: 4040 h - 405f h each of the 32 hdlc channels has a 7-bit command vector that resides in the corresponding address of the command ram. the structure of a command vector is as follows: note: accesses to these registers are possible only if register bit hcr:dspctrl = 1 ?x? = unused 15 14 13 12 11 10 9 8 xx x xxxxx 76 5 43210 x dbsel recres txcmd(2:0) crc idle dbsel d- or b-channel select 0 = indication for a b-channel. hdlc protocol is performed on all 8 data bits 1 = indication for a d-channel. hdlc protocol is performed only on the 2 msb data bit in the receive input buffer and transmit output buffer recres receiver reset 0 = normal operation 1 = reset the hdlc receiver txcmd(2:0) transmit command 000= end transmition 001= start transmission at the first bit of the d-channel 010= start transmission at the second bit of the d-channel 011= start transmitting a flag (beginning with the fifth bit of the flag, since ?0111? is automatically inserted) 100= abort transmission note: other combinations are reserved crc crc enable 0 = crc checking algorithm off
delic register description preliminary data sheet 6-36 2003-08 note: in the receive direction, the only function of the command vector is to indicate whether the channel is a d-channel or a b-channel, and whether to use crc decoding or not. the main function of the command vector is to control the flow of time slots in the transmit direction. 6.2.5.4 channel status vector hcsv registers read addresses: 40a0 h - 40bf h reading a channel from the receive output buffer and writing to a channel in the transmit input buffer is done according to the channel?s status vector in the transmit output buffer. this vector contains 7 flags: note: accesses to these registers are possible only if register bit hcr:dspctrl = 1 ?x? = not used 1 = crc checking algorithm on idle idle mode 0 = transmit ?ones? over an idle channel - the unshared flag mode 1 = transmit ?flags? over an idle channel - the shared flag mode 15 14 13 12 11 10 9 8 xxxxxxxx 76543210 x flag empty full abort stop crc no no not octet 0 = normal operation 1 = the last bits of a message have not filled an octet (8 bits) crc crc error 0 = no crc error in received message 1 = crc error was detected in the received message stop stop indication 0 = normal operation
delic register description preliminary data sheet 6-37 2003-08 1 = hdlcu has detected an end of message flag in the receive direction. the dsp must read the octet in the receive output buffer before the next message start flag is detected abort abort indication 0 = normal operation 1 = the dsp has detected an incoming abort message (7 consecutive ?1s?). the stop flag is also set to 1. this means that the dsp should ignore the current message being transmitted over the channel in question and report to the external microcontoller full receive buffer full indication 0 = normal operation 1 = indicates that the receive output buffer has a newly processed octet in it. the dsp must read this octet before starting the next processing session, otherwise it might be lost. empty transmit buffer empty 0 = the transmit buffer is full. 1 = the transmit buffer is empty. the current time slot in the transmit input buffer has been fully processed by the hdlcu. the transmit input buffer is ready to receive the next octet of the message by the dsp. note: the dsp must put a new octet into the buffer before starting the next processing session, otherwise the same octet will be read again. flag status vector flag 0 = ignore the status vector and do not read or write on this channel 1 = read the channel?s status vector and process accordingly note: flag will go to ?1? as soon as empty or full go to ?1?.
delic register description preliminary data sheet 6-38 2003-08 6.2.6 ghdlc register description 6.2.6.1 ghdlc test/ normal mode register gtest register write address: d0c0 h reset value: 0001 h note: as gtest has a reset value of 01h this register has to set to 0 to enable the ghdlcu 6.2.6.2 ghdlc channel mode register gchm register write address: d0c1 h reset value: 0000 h 15 14 13 12 11 10 9 8 x xxxxxxx 7 6543210 x xxxxxxtest chmod1..0 channel mode 0 = normal operation mode 1 = test mode 15 14 13 12 11 10 9 8 x xxxxxxx 7 6543210 x xxxxxchmod(1..0) chmod1..0 channel mode 00 = channel 0 used up to 16.384 mhz
delic register description preliminary data sheet 6-39 2003-08 6.2.6.3 ghdlc interrupt register gint register read address: d0d4 h reset value: 0000 h 6.2.6.4 ghdlc fsc interrupt control register gfint register read address: d0d3 h reset value: 0000 h 01 = 2 channels (ch 0+3) used up to 8.192 mhz 10 = 4 channels (ch 0..3) used up to 4.096 mhz 11 = reserved 15 14 13 12 11 10 9 8 xxxxxxxx 76543210 x x x x int3 int2 int1 int0 intn bits interrupt indication for ghdlc channel n (= 0..3) 0 = normal operation 1 = ghdlc interrupt has occurred 15 14 13 12 11 10 9 8 xxxxxxxx 76543210 x x x x fint3 fint2 fint1 fint0 fintn fsc interrupt control ghdlc channel n (= 0..3)
delic register description preliminary data sheet 6-40 2003-08 6.2.6.5 ghdlc receive channel status registers 0..3 grsta register 0 read address: d0c2 h grsta register 1 read address: d0c3 h grsta register 2 read address: d0c4 h grsta register 3 read address: d0c5 h reset value: 001f h 0 = fsc rising edge causes a receiver interrupt only if a full interrupt has not occurred during the previous frame 1 = fsc rising edge causes a receiver interrupt regardless whether or not a full interrupt occurred during the previous frame 15 14 13 12 11 10 9 8 x x x x x x colld under 76543210 empty over full rbfill(4:0) rbfill(4:0) receive buffer fill indicates to the dsp the currently available number of bytes - 1 in the receive buffer full receive buffer full 0 = no receive buffer full indication 1 = receive buffer block of the ghdlc is full. the blocks have been switched. over buffer overrun 0 = no buffer overrun indication 1 = two consecutive full interrupts were received without a ghdlc access to the status register in between, i.e. a buffer was missed. empty transmit buffer empty 0 = no transmit buffer empty indication 1 = the transmit buffer block currently being transmitted over the ghdlc channel has been emptied
delic register description preliminary data sheet 6-41 2003-08 note: reading the register grsta resets its bits to the default value. 6.2.6.6 ghdlc receive data and status to each data byte in the receive buffer 4 flag bits are appended rxdat registers read address: 2000 h -203f h . under buffer underrun 0 = no buffer underrun indication 1 = a buffer containing an uncomplete message has been emptied without a continuation of the message in the other buffer colld collision detected 0 = no collision detection indication 1 = collision detected during transmission. the message needs to be re-sent. note: only relevant in hdlc-mode, if one device does not operate conform to the hdlc protocol definition 15 14 13 12 11 10 9 8 abort end crc no x x x x 76543210 rdat7..0 no not octet 0 = received message is a multiple of eight bits 1 = received message is not a multiple of eight bits crc crc error flag 0 = received byte contains no crc error flag. 1 = received byte contains a crc error flag. a crc error was detected in the received frame. end end flag 0 = received byte contains no end flag 1 = received byte contains an end flag
delic register description preliminary data sheet 6-42 2003-08 6.2.6.7 ghdlc mode registers gmod register 0 write address: d0c6 h gmod register 1 write address: d0c7 h gmod register 2 write address: d0c8 h gmod register 3 write address: d0c9 h reset value: 0140 h abort abort flag 0 = received byte contains no abort flag 1 = received byte contains an abort flag rd7..0 received data byte 15 14 13 12 11 10 9 8 xxxxxxedgete 76543210 class colld ppod iftf opmod(1:0) crcmod(1:0) crcmod(1:0) crc mode 00 = crc algorithm disabled 01 = 16-bit crc algorithm (x 16 +x 12 +x 5 +1) 10 = 32-bit crc algorithm (x 31 +x 26 +x 23 +x 22 +x 16 +x 12 +x 11 +x 10 +x 8 +x 7 +x 5 +x 4 +x 2 +x 1 +1) 11 = reserved opmod(1:0) operational mode programs the mode of the ghdlc channel 00 = hdlc mode 01 = reserved 10 = asynchronous mode (enables accesses to register gasync) 11 = reserved iftf interframe time fill 0 = sequence of ?1s? is used as interframe time fill characters
delic register description preliminary data sheet 6-43 2003-08 6.2.6.8 ghdlc channel transmit command registers gtcmd register 0 write address: d0ca h gtcmd register 1 write address: d0cc h gtcmd register 2 write address: d0ce h gtcmd register 3 write address: d0d0 h reset value: 0000 h 1 = flags (7e h ) are used as interframe time fill characters ppod push-pull / open-drain configuration 0 = open-drain 1 = push-pull colld collision detection 0 = collision detection disabled 1 = arbitration between several ghdlc on a bus is done using collision detection class priority class assignment 0 = channel has priority class 8 1 = channel has priority class 10 te transmit enable 0 = transmit line is only enabled during the transmission of a message including opening and closing flags 1 = transmit line is always enabled edge edge programming for receive data sampling 0 = receiver samples data on rising edge of the line clock 1 = receiver samples data on falling edge of the line clock 15 14 13 12 11 10 9 8 xxxxxxxx 76543210 x stop txcmd tbfill(4:0)
delic register description preliminary data sheet 6-44 2003-08 6.2.6.9 async control register gasync register read/ write address: d0d2 h reset value: 0000 accesses to register gasync: accesses to the different bits of this register are only possible in async mode of the corresponding ghdlc channel (see ?ghdlc mode registers? on page 42.). tbfill(4:0) transmit buffer fill indicates to the ghdlc unit the currently available number of bytes - 1 in the transmit buffer. txcmd transmission command 0 = transmission is not started 1 = start transmission stop stop command 0 = message continues in the next buffer 1 = end of the message is in this buffer 15 14 13 12 11 10 9 8 xxxxxxxx 76543210 ioport(7..0) ioport bits writing a "1" to the bit position sets the port pin below reading from the bit position indicates the current state of the port pin below bit 0 ltxd0 lrxd0 bit 1 ltxd1 lrxd1 bit 2 ltxd2 lrxd2 bit 3 ltxd3 lrxd3 bit 4 lrts0 lcts0 bit 5 lrts1 lcts1 bit 6 lrts2 lcts2 bit 7 lrts3 lcts3
delic register description preliminary data sheet 6-45 2003-08 note: ghdlc channels 3..1 are only accessible, if respective bits in register muxctrl are set. 6.2.6.10 lclk0 control register lclk0 control register (glclk0) read/write address: d08a h reset value: 0000 h note: ?x? = unused bits, read as 0. 15 14 13 12 11 10 9 8 xxxxx xxx 76543 210 x x x x x lclk0en lclk0(1:0) lclk0en lclk0 output enable 0 = lclk0 is input (default) 1 = lclk0 is driven outward via lclk0 pin lclk0(1:0) lclk0 output clock rate note: this option is valid only when lclk0 is output. when lclk0 is input the frequency is determined externally. 00 = 2.048 mhz (default) 01 = 4.096 mhz 10 = 8.192 mhz 11 = 16.384 mhz
delic register description preliminary data sheet 6-46 2003-08 6.2.6.11 lclk1 control register lclk1 control register (glclk1) read/write address: d08b h reset value: 0000 h note: ?x? = unused bits, read as 0. 15 14 13 12 11 10 9 8 xxxxx xxx 76543 210 x x x x x lclk1en lclk1(1:0) lclk1en lclk1 output enable 0 = lclk1 is input (default) 1 = lclk1 is driven outward via lclk1 pin lclk1(1:0) lclk1 output clock rate note: this option is valid only when lclk1 is output. when lclk1 is input the frequency is determined externally. 00 = 2.048 mhz (default) 01 = 4.096 mhz 10 = 8.192 mhz 11 = 16.384 mhz
delic register description preliminary data sheet 6-47 2003-08 6.2.6.12 lclk2 control register lclk2 control register (glclk2) read/write address: d08c h reset value: 0000 h note: ?x? = unused bits, read as 0. 15 14 13 12 11 10 9 8 xxxxx xxx 76543 210 x x x x x lclk2en lclk2(1:0) lclk2en lclk2 output enable 0 = lclk2 is input (default) 1 = lclk2 is driven outward via lclk2 pin lclk2(1:0) lclk2 output clock rate note: this option is valid only when lclk2 is output. when lclk2 is input the frequency is determined externally. 00 = 2.048 mhz (default) 01 = 4.096 mhz 10 = 8.192 mhz 11 = 16.384 mhz
delic register description preliminary data sheet 6-48 2003-08 6.2.6.13 lclk3 control register lclk3 control register (glclk3) read/write address: d08d h reset value: 0000 h note: ?x? = unused bits, read as 0. 15 14 13 12 11 10 9 8 xxxxx xxx 76543 210 x x x x x lclk3en lclk3(1:0) lclk3en lclk3 output enable 0 = lclk3 is input (default) 1 = lclk3 is driven outward via lclk3 pin lclk3(1:0) lclk3 output clock rate note: this option is valid only when lclk3 is output. when lclk3 is input the frequency is determined externally. 00 = 2.048 mhz (default) 01 = 4.096 mhz 10 = 8.192 mhz 11 = 16.384 mhz
delic register description preliminary data sheet 6-49 2003-08 6.2.6.14 muxes control register muxctrl register oak: read/write address: d14a h reset value: 0000 h 15 14 13 12 11 10 9 8 x xxxxxxx 7 6543210 x xxxxpmux1pmux0imux imux 0 = iom-2000 pins are used for the iom-2000 interface 1 = iom-2000 pins are used for the ghdlc cha. 1 pmux0 0 = pcm ports 0 & 2 pins are used for pcm 1 = pcm ports 0 & 2 pins are used for ghdlc cha. 2 pmux1 0 = pcm ports 1 & 3 pins are used for pcm 1 = pcm ports 1 & 3 pins are used for ghdlc cha. 3
delic register description preliminary data sheet 6-50 2003-08 6.2.7 dcu register description 6.2.7.1 interrupt mask register imask register read/write address: d002 h reset value: 0000 h note: the unused bits (x) are read as ?0?. 6.2.7.2 status event register steve register read address: d003 h reset value: 0000 h 15 14 13 12 11 10 9 8 xxxxxxxx 76543210 xxxxxxximask imask ghdlc interrupt mask 0 = ghdlc interrupt disabled 1 = ghdlc interrupt enabled 15 14 13 12 11 10 9 8 xxxxxxxx 76543210 xxxxxpfsfscfp pfs pfs status bit 0 = normal operation 1 = pfs rising edge has occurred (reset by dsp read access)
delic register description preliminary data sheet 6-51 2003-08 note: unused bits (?x?) are read as ?0?. 6.2.7.3 statistics counter register statc register read/write address: d004 h reset value: unchanged reset value: unchanged upon chip reset, but reset upon fsc detection if statc was read by the dsp since last occurence of fsc. note: the unused bits (x) are read as ?0?. fsc fsc status bit 0 = normal operation 1 = fsc rising edge has occurred (reset by dsp read access) fp fsc & pfs status bit 0 = normal operation 1 = both fsc and pfs rising edges have occurred, i.e. bits pfs and fsc are set (reset by dsp read access) 15 14 13 12 11 10 9 8 xxxxxxxx 76543210 statc(7:0) statc (7:0) statistics counter value
delic register description preliminary data sheet 6-52 2003-08 6.2.7.4 statistics register stati register read/write address: d005 h reset value: 0000 h note: the unused bits (x) are read as ?0?. 6.2.8 p configuration registers 6.2.8.1 p interface configuration register mcfg register dsp: read dsp address: d148 h p: read/write p high address: none p low address: 48 h reset value: 00 h 15 14 13 12 11 10 9 8 xxxxxxxx 76543210 msc(7:0) msc(7:0) max. statistics count 15 14 13 12 11 10 9 8 xxxxxxxmode 76543210 drqlv irqlv irqmo imask iack pec fb dma dma dma mode enabled 0 = no dma
delic register description preliminary data sheet 6-53 2003-08 1 = dma enabled fb fly-by mode 0 = memory-to-memory mode used for dma transfers 1 = fly-by mode used for dma transfers pec pec transfers enable 0 = no pec transfers 1 = pec transfers are supported (for connection of c16x p) iack interrupt acknowledge mode 0 = interrupt vector is provided to cpu after 1st iack pulse. 1 = interrupt vector is provided to cpu after 2nd iack pulse. imask interrupt mask 0 = ireq pin is disabled 1 = ireq pin is enabled irqmo ireq pin mode 0 = open-drain mode 1 = push-pull mode irqlv ireq pin level 0 = low active 1 = high active drqlv dreqr/dreqt pins level 0 = high active 1 = low active mode p interface mode contains the value of mode input pin sampled by rising edge of reset note: this signal is hardwired. 0 = intel/siemens mode 1 = motorola mode
delic register description preliminary data sheet 6-54 2003-08 6.2.8.2 device version register vdev register p: read p address: 6a h reset value: none (hardwired) 6.2.8.3 interrupt vector register ivec register dsp: read/ write dsp address: d168 h p: read p high address: none p low address: 68 h reset value: unchanged 76543210 vdev(7:0) vdev device version contains the information about the device status. 1 h delic version 1.1 2 h delic version 2.1 76543210 ivec(7:0) ivec7..0 interrupt vector contains the interrupt vector address that is output during an inta cycle of the p
delic register description preliminary data sheet 6-55 2003-08 6.2.9 p mailbox registers description 6.2.9.1 p command register mcmd register dsp: read dsp address: d140 h p: write p address: 40 h reset value: 00 h 6.2.9.2 p mailbox busy register mbusy register dsp: write dsp address: d141 h p: read p high address: 41 h p low address: none reset value: 00 h 76543210 mcmd mcmd p command contains the p command (8-bit opcode) to the delic. 15 14 13 12 11 10 9 8 mbusyx x x xxxx 76543210 xxxxxxxx mbusy p mailbox busy bit 0 = mailbox is available for the external p. the p may write a command to mcmd.
delic register description preliminary data sheet 6-56 2003-08 6.2.9.3 p mailbox generic data register mgen register dsp: read dsp address: d144 h dsp high: d143 h dsp low: d142 h p: write p high: 43 h p low: 42 h reset value: unchanged 1 = mailbox is blocked for the external p. the p may not write a command to mcmd. note: mbusy is automatically set each time a command is written to mcmd by the p. mbusy is reset automatically by a direct oak write operation to the mbusy register. 15 14 13 12 11 10 9 8 mgen(15..8) 76543210 mgen(7..0) mgen (15..0) p mailbox generic data (16 bits)
delic register description preliminary data sheet 6-57 2003-08 6.2.9.4 p mailbox (general and dma mailbox) data registers mdtn register (n=0..7) dsp: read addr. see table on page 6-6 tdtn/ mdtn+8 register (n=0..7) p: write reset value: unchanged note: the 16 data registers (mdt1..7, tdt0/mdt8..tdt7/mdt15) have the same structure. the addresses are displayed in the register map (page 6-6, page 6-7). 6.2.9.5 dsp command register ocmd register dsp: write dsp address: d160 h p: read p address: 60 h reset value: 00 h 15 14 13 12 11 10 9 8 mdtn(15..8) 76543210 mdtn(7..0) mdtn (15..0) p mailbox data (each byte is addressed seperately by the external p) 76543210 ocmd ocmd dsp command contains the dsp command/ indication (8-bit opcode) to the delic.
delic register description preliminary data sheet 6-58 2003-08 6.2.9.6 dsp mailbox busy register obusy register dsp: read dsp address: d161 h p: read/ write p high address: 61 h p low address: none reset value: 00 h 15 14 13 12 11 10 9 8 obusyx x x xxxx 76543210 xxxxxxxx obusy dsp mailbox busy bit 0 = mailbox is available for the dsp. the dsp may write a command/ indicationto ocmd. 1 = mailbox is blocked for the dsp. the dsp may not write a command/ indication to ocmd. note: obusy is automatically set each time a command/ indication is written to ocmd by the dsp. obusy is reset automatically by a direct p write operation to the obusy register
delic register description preliminary data sheet 6-59 2003-08 6.2.9.7 dsp mailbox generic data register ogen register dsp: write dsp address: d164 h dsp high: d163 h dsp low: d162 h p: read p high: 63 h p low: 62 h reset value: unchanged 6.2.9.8 dsp mailbox (general and dma mailbox) data registers odtn register (n= 0..15) dsp: write addr. see table on page 6-7 rdtn/ odtn+8 register (n=0..7) p: read reset value: unchanged ( note: the 16 data registers (odt1..7, rdt0/odt8..rdt7/odt15) have the same structure. the addresses are displayed in the register map (page 6-6, page 6-7). 15 14 13 12 11 10 9 8 ogen(15..8) 76543210 ogen(7..0) ogen 15..0 dsp mailbox generic data (16 bits) 15 14 13 12 11 10 9 8 odtn(15..8) 76543210 odtn(7..0) odtn (15..0) dsp mailbox data (each byte is addressed seperately by the external p)
delic register description preliminary data sheet 6-60 2003-08 6.2.10 dma mailbox registers description 6.2.10.1 dma mailbox transmit counter register dtxcnt register dsp: read/write address: d150 h reset value: 0000 h note: writing to txcnt initiates a dma transfer of txcnt bytes to the dma tx mailbox. this register value does not change during the current transfer. 6.2.10.2 dma mailbox receive counter register drxcnt register dsp: read/write address: d170 h reset value: 0000 h note: writing to rxcnt initiates a dma transfer of rxcnt bytes to the dma rx mailbox. this register value does not change during the current transfer. 15 14 13 12 11 10 9 8 xxxxxxxx 76543210 xxxx txcnt(3:0) 15 14 13 12 11 10 9 8 xxxxxxxx 76543210 xxxx rxcnt(3:0)
delic register description preliminary data sheet 6-61 2003-08 6.2.10.3 dma mailbox interrupt status register dinsta register dsp: read address: d152 h reset value: 0000 h contains the status of the dma mailbox. 15 14 13 12 11 10 9 8 xxxxxxxx 76543210 xxxx insta(3:0)
delic register description preliminary data sheet 6-62 2003-08 6.2.11 clock generator register description 6.2.11.1 pdc control register pdc control register (cpdc) read/write address: d080 h reset value: 0000 h note: ?x? = unused bits, read as 0. 6.2.11.2 pfs control register pfs control register (cpfs) read/write address: d081 h reset value: 0001 h note: ?x? = unused bits, read as 0. 15 14 13 12 11 10 9 8 xxxxxxxx 76543210 xxxxxx pdc(1:0) pdc(1:0) pdc frequency selection (only in master mode when pdc is output) 00 = pdc = 2.048 mhz (default) 01 = pdc = 4.096 mhz 10 = pdc = 8.192 mhz 11 = pdc = 16.384 mhz 15 14 13 12 11 10 9 8 xxxxxxxx 76543210 xxxxxxxpfs pfs pfs frequency selection (selectable in slave mode when pfs is input; in master mode pfs = 8 khz) 0 = pfs = 4 khz
delic register description preliminary data sheet 6-63 2003-08 note: when the pfs is output, its frequency is always 8 khz, therefore this bit should be left in its reset-value ('1') and not to be changed. the direction of pfs and pdc: input (slave) or output (master) is determined by the master/slave strap (dreqr pin) during reset. 6.2.11.3 clkout control register clkout control register (clkout) read/write address: d082 h reset value: 0008 h note: ?x? = unused bits, read as 0. 1 = pfs = 8 khz (default) 15 14 13 12 11 10 9 8 xxxx x xxx 7654 3 210 x x x x clkouten clkout clkouten clkout pin enable 0 = clkout pin is in tri-state. 1 = clkout pin is active. (default) clkout clkout pin frequency 000 = 2.048 mhz (default) 001 = 4.096 mhz 010 = 8.192 mhz 011 = 15.36 mhz 100 = 16.384 mhz
delic register description preliminary data sheet 6-64 2003-08 6.2.11.4 dcxo reference clock select register refsel register (crefsel) read/write address: d083 h reset value: 0000 h note: ?x? = unused bits, read as 0 this register controls the selection of the source of the dcxo 8khz reference clock 15 14 13 12 11 10 9 8 xxxxxxxx 76543210 xxxxrefsel en refsel(2:0) refselen dcxo reference clock enable 0 = the reference clock is disabled (default) 1 = the reference clock is enabled refsel(2:0) dcxo reference clock select 000 = dxclk/192 (default) 001 = xclk/256 010 = xclk 011 = refclk (when input) 100 = refclk (when input)/64 101 = pfs (when input)
delic register description preliminary data sheet 6-65 2003-08 6.2.11.5 refclk control register refclk control register (crefclk) read/write address: d084 h reset value: 0003 h note: ?x? = unused bits, read as 0. refclk may be configured as an input or as an output. when configured as an input, it may be used as a source for the on-chip dcxo 8khz reference clock. this option is handled by the dcxo reference clock select register (crefsel). when configured as an output it is derived from xclk input pin. in order to drive refclk, xclk may be divided by 256, 192, 4, 3 or 1. 15 14 13 12 11 10 9 8 xxxx x xxx 7654 3 210 x x x x refclken refdiv(2:0) refclken refclk pin output enable 0 = refclk is input, the pad is not output enabled 1 = refclk is output refdiv(2:0) refclk pin output divider selection this determines the value by which the xclk maximum clock of 2.048 mhz is divided internally. 000 = division by 256 001 = division by 192 010 = division by 4 011 = division by 3 (default) 100 = division by 1
delic register description preliminary data sheet 6-66 2003-08 6.2.11.6 dcl_2000 control register dcl_2000 control register (cdcl2) read/write address: d085 h reset value: 0004 h note: ?x? = unused bits, read as 0. 6.2.11.7 dcl control register dcl control register (cdcl) read/write address: d086 h reset value: 000b h note: ?x? = unused bits, read as 0. 15 14 13 12 11 10 9 8 xxxxxxxx 76543210 xxxxxdcl2endcl2(1:0) dlc2en dcl_2000 clock enable 0 = dcl_2000 clock is disabled 1 = dcl_2000 clock is enabled (default) dcl2(1:0) dcl_2000 clock rate 00 = 3.072 mhz (default) 01 = 6.144 mhz 10 = 12.288 mhz 15 14 13 12 11 10 9 8 xxxxxxxx 76543210 x x x x dclen dcl(2:0) dclen dcl clock enable 0 = dcl is disabled
delic register description preliminary data sheet 6-67 2003-08 6.2.11.8 fsc control register fsc control register (cfsc) read/write address: d087 h reset value: 0002 h note: ?x? = unused bits, read as 0. 1 = dcl is enabled (default) dcl(2:0) dcl clock rate 000 = 384 khz 001 = 768 khz 010 = 1536 khz 011 = 2048 khz (default) 100 = 4096 khz 15 14 13 12 11 10 9 8 xxxxxxxx 76543210 x x x x ifscd efsc fscen fscsh fscen fsc clock enable 0 = fsc is disabled (stuck at '0') 1 = fsc is enabled (default) fscsh short fsc pulse 0 = the next fsc pulse will be longer than 2 dcl cycles (default) 1 = the next fsc pulse will be shorter than 2 dcl cycles (short fsc) efscd external fsc delay 0 = no delay between fsc and dcl rising edge 1 = fsc rising edge is delayed by one clk61 clock (16 ns) relative to dcl/ dcl2000 ifscd internal fsc delay (only valid of cstrap: bit0 = 1) 0 = no delay between fsc and dcl rising edge
delic register description preliminary data sheet 6-68 2003-08 note: if only one short fsc pulse is needed, this bit should be reset to '0' by the delic software, after the next fsc rising edge detection (after the begining of the next frame). it is not executed automatically by the hardware. 6.2.11.9 l1_clk control register l1_clk control register (cl1clk) read/write address: d088 h reset value: 0000 h note: ?x? = unused bits, read as 0. 1 = fsc rising edge is delayed by one clk61 clock (16 ns) relative to dcl/ dcl2000 15 14 13 12 11 10 9 8 xxxxxx x x 765432 1 0 x x x x x x l1clkdis l1clk l1clken l1_clk disable 0 = l1_clk is enabled (default) 1 = l1_clk is disabled l1clk l1_clk clock rate 0 = 7.68 mhz (default) 1 = 15.36 mhz
delic register description preliminary data sheet 6-69 2003-08 6.2.11.10 pfs sync register pfs sync register (cpfssy) read/write address: d089 h reset value: 0000 h note: ?x? = unused bits, read as 0. during read cycle the 2 lsbs are driven by the the pfs-sync state-machine's state bits. this is needed only for testing. the pfs-sync signal actually resets the 61.44 mhz-clock-division-chain. the pfs- sync signal activated with the pfs-rising edge detection, but only when the internal-reset is activated or after a "pfs-sync" instruction was carried out by the oak. the goal of reseting the 61.44mhz-clock-division-chain by pfs-sync, is to lead to a situation in which fsc rises with pfs. after the initial reset by the pfs-sync a small- and flexible phase difference is maintained by the dcxo-pll. a write access to pfs-sync register, resets the 61mhz clock-division chain, including fsc, by the next pfs rising-edge detection. this is true only if the write access was carried-out before the falling edge of pfs. if the write-access comes after the falling edge of pfs, the acctuall sync operation will not be carried out by the next pfs rising-edge, but with one that will come after it. the written value does not make any difference. 6.2.11.11 realtime counter register rt counter register (crtcnt) read address: d08e h reset value: 0000 h this 18-bit counter counts 8 khz cycles. it is used by the software to time the handling of required tasks. one period of the counter (counting from 0000h to ffffh and back 15 14 13 12 11 10 9 8 xxxxxxxx 76543210 x x x x pfssync(1:0) 15 14 13 12 11 10 9 8 rtcount(15:8) 76543210 rtcount(7:0)
delic register description preliminary data sheet 6-70 2003-08 to 0000h) is 32.768 sec. only the 16 msbs of the counter may be read by the oak, therefore the actuall resolution is 0.5 ms. . 6.2.11.12 strap status register strap status register (cstrap) read/ write address: d08f h reset value: xxxx xxxx xxxx xx10 b note: ?x? = unused bits, read as 0. rtcount(15:0) the 16 msbs of the realtime counter 15 14 13 12 11 10 9 8 xxxxx strap(10:8) 7654321 0 strap(7:0) strap (10:0) this register enables the oak to read the straps values, as sampled during reset bit 10 pcm clock master strap bit 9:7 test mode strap bit 6 emulation boot strap bit 5 pll bypass strap bit 4 dsp pll power-down strap bit 3 boot strap bit 2 reset counter bypass strap bit 1 dcxo fast-synchronization enable 0 = 1 = linear (slow) synchronization (for dect applications) fast synchronization (default) bit 0 internal source clock strap 0 = 1 = pfs, pdc, dcl, fsc, dcl2000 are delayed by some ns (default) pfs, pdc, dcl, fsc, dcl2000 are not delayed
delic package outlines preliminary data sheet 7-1 2003-08 7 package outlines p-tqfp-100-1 (plastic thin quad flat package) gpm05247 smd = surface mounted device sorts of packing package outlines for tubes, trays etc. are contained in our data book ?package information?. dimensions in mm
delic peb 20571 electrical characteristics preliminary data sheet 8-1 2003-08 8 electrical characteristics 8.1 absolute maximum ratings note: stresses above those listed here may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. 8.2 operating range note: in the operating range, the functions given in the circuit description are performed. parameter symbol limit values unit storage temperature t stg ? 65 to 150 c ic supply voltage v dd ? 0.3 to 4.6 v dc input voltage (except i/os) v i ? 0.3 to 6.0 v dc output voltage (including i/os); output in high or low state v o ? 0.3 to v dd + 0.3 v dc output voltage (including i/os); output in tri-state v i, v o ? 0.3 to 6.0 v esd robustness 1) hbm: 1.5 k ? , 100 pf 1) according to mil-std 883d, method 3015.7 and esd ass. standard eos/esd-5.1-1993. the pins (tbd) are not protected against voltage stress > (tdb) v (versus v s or gnd). the (tbd) performance prohibits the use of adequate protective structures. v esd,hbm 1000 v parameter symbol limit values unit min. max. power supply voltage v dd 3.13 3.47 v ground v ss 00v voltage applied to input pins v in 05.5v voltage applied to output or i/o pins outputs enabled outputs high-z v out v out 0 0 v dd 5.5 v v operating temperature peb pef t a t a 0 -40 70 85 c c input transition rise or fall time ? t/ ? v010ns/v
delic peb 20571 electrical characteristics preliminary data sheet 8-2 2003-08 8.3 dc characteristics note: the listed characteristics are ensured over the operating range of the integrated circuit. typical characteristics specify mean values expected over the production spread. if not otherwise specified, typical characteristics apply at t a = 25 c and the given supply voltage. parameter symbol limit values unit test condition min. max. high-level input voltage v ih 2.0 v dd + 0. 3 vv out >= v oh (min) low-level input voltage v il ? 0.3 0.8 v v out <= v ol (max) high-level output voltage (all pins except dd0, dd1, dx, ltxd0, txd0, txd1) v oh 2.4 v v dd = min, i oh = ?2 ma low-level output voltage (all pins except dd0, dd1, dx, ltxd0, txd0, txd1) v ol 0.4 v v dd = min, i ol =2 ma high-level output voltage (pins dd0, dd1, dx, ltxd0, txd0, txd1) v oh 2.4 v v dd = min, i oh = ?7 ma low-level output voltage (pins dd0, dd1, dx, ltxd0, txd0, txd1) v ol 0.4 v v dd = min, i ol =7 ma input leakage current i il 1 a v dd =3.3v, gnd = 0 v; all other pins are floating; v in =0v output leakage current i oz 1 a v dd =3.3v, gnd = 0 v; v out =0v avg. power supply current i cc (av) tbd ma v dd =3.3v, t a =25 c: pdc = 8 mhz dsp @ 61.44 mhz
delic peb 20571 electrical characteristics preliminary data sheet 8-3 2003-08 8.4 capacitances 8.5 recommended 16.384 mhz crystal parameters parameter symbol limit values unit notes min. max. input capacitance i/o capacitance c in c i/o 7 7 pf pf f c =1 mhz, the pins, which are not under test, are connected to gnd output capacitance c out 10 pf crystal input capacitance (pin clk16-xi) c xin 3.3 (tbd) pf crystal output capacitance (pin clk16-xo) c xout 3.3 (tbd) pf parameter symbol limit values unit test condition min. max. motional capacitance c 1 25 ff shunt capacitance c 0 7pf external load capacitance c l 15 pf resonance resistance r r 30 ? frequency calibration tolerance 150 ppm
delic timing diagrams preliminary data sheet 9-1 2003-08 9 timing diagrams 9.1 general for ttl and cmos voltage levels refer to the relevant jedec specifications, e.g. to jedec8-a for 3v/3.3v devices which are 5v compatible. note: the complete ac characteristics will be provided after the electrical characterization of the device. all timing shown are preliminary. 9.2 p access timing p accesses of the delic are performed by an activation of the address and cs . by driving the mode pin ?high? the user selects motorola mode, by driving it ?low? - intel/infineon mode. the pin is sampled during the rising edge of reset . in intel/infineon mode, a distinction is needed between working in multiplexed address/data bus mode and de-multiplexed address and data bus mode. in motorola mode, only de-multiplexed buses are used. the selection between multiplexed and de-multiplexed bus configurations is done by using the ale pin. 9.2.1 p access timing in motorola mode in this mode r/w distinguishes between read and write interactions, and ds is used for timing.
delic timing diagrams preliminary data sheet 9-2 2003-08 note: ds x cs is active (low) when both, ds and cs , are active (low) figure 9-1 write cycle in motorola mode table 9-1 timing for write cycle in motorola mode parameter symbol limit values unit test condition min. max. r/w setup time before ds x cs rising edge t srws 15 ns output load capacity of 50 pf r/w hold time after ds x cs rising edge t hrws 5ns a-bus setup time before ds x cs rising edge t sas 15 ns a-bus hold time after ds x cs rising edge t has 5ns d-bus setup time before ds x cs rising edge t sds 12 ns d-bus hold time after ds x cs rising edge t hds 10 ns ds x cs pulse width t ws 15 ns r/w a d ds x cs t srws t sas t sds t hrws t has t ws t hds
delic timing diagrams preliminary data sheet 9-3 2003-08 note: ds x cs is active (low) when both, ds and cs are active (low) figure 9-2 read cycle in motorola mode 9.2.2 p access timing in intel/infineon mode in this mode driving rd ?low? causes a read access, driving wr ?low? causes a write access. timing for demultiplexed bus in de-multiplexed bus configuration, ale must be driven ?high?. table 9-2 timing for read cycle in motorola mode parameter symbol limit values unit test condition min. max. r/w setup time before ds x cs falling edge t srws 0 ns output load capacity of 50 pf r/w hold time after ds x cs rising edge t hrws 5ns a-bus valid to d-bus valid t dad 020ns ds x cs falling edge to d-bus t dsd 020ns d-bus float after ds x cs rising edge t dsdh 015ns a r/w dsxcs d t hsrw t srws t dsd t dad t dsdh
delic timing diagrams preliminary data sheet 9-4 2003-08 figure 9-3 write cycle in intel/infineon de-multiplexed mode table 9-3 timing for write cycle in intel/infineon demultiplexed mode parameter symbol limit values unit test condition min. max. a-bus setup time before wr rising edge t saw 12 ns output load capacity of 50 pf a-bus hold time after wr rising edge t haw 5ns cs setup time before wr rising edge t scw 12 ns cs hold time after wr rising edge t hcw 5ns d-bus setup time before wr rising edge t sdw 12 ns d-bus hold time after wr rising edge t hdw 10 ns wr pulse width t ww 15 ns wr a cs d t sdw t saw t hdw t scw t haw t hcw t ww
delic timing diagrams preliminary data sheet 9-5 2003-08 note: rd x cs is active (low) when both rd and cs are active (low) figure 9-4 read cycle in intel/infineon de-multiplexed mode table 9-4 timing for read cycle in intel/infineon de-multiplexed mode parameter symbol limit values unit test condition min. max. a-bus valid to d-bus valid t dad 0 20 ns output load capacity of 50 pf rd x cs falling edge to d-bus t drd 020ns d-bus float after rd x cs rising edge t drdh 015ns a rdxcs d t drd t dad t drdh
delic timing diagrams preliminary data sheet 9-6 2003-08 timing for multiplexed bus in this mode the ale pin is used to lock the address send via the multiplexed a/d bus. figure 9-5 write cycle in intel/infineon multiplexed mode table 9-5 timing for write cycle in intel/infineon multiplexed mode parameter symbol limit values unit test condition min. max. a-bus setup time before ale falling edge t sal 12 ns output load capacity of 50 pf a-bus hold time after ale falling edge t hal 5ns ale pulse width t wl 10 ns cs setup time before wr rising edge t scw 12 ns cs hold time after wr rising edge t hcw 5ns d-bus setup time before wr rising edge t sdw 12 ns d-bus hold time after wr rising edge t hdw 10 ns ale hold time after wr rising edge t hlw 5ns wr pulse width t ww 15 ns wr cs ad ale t sal t hal t scw t hcw t sdw t hdw t hlw t wl address data t ww
delic timing diagrams preliminary data sheet 9-7 2003-08 figure 9-6 read cycle in intel/infineon multiplexed mode 9.3 interrupt acknowledge cycle timing the ireq (interrupt request) output signal of the delic is activated upon a dsp write operation to the ocmd register (oak mailbox command register). this operation sets the oak mailbox busy bit (obusy), which drives directly the ireq output signal. the ireq signal may be masked, by programming the mask bit within the p interface control register (upcr). the microprocessor may force the delic to drive the interrupt vector over the data bus by activation of the interrupt acknowledge input signal (iack ). table 9-6 timing for read cycle in intel/infineon multiplexed mode parameter symbol limit values unit test condition min. max. ale low before rd x cs falling edge t hrl 5 ns output load capacity of 50 pf ale hold time after rd x cs rising edge t hlr 5ns ale pulse width t wl 10 ns a-bus setup time before ale falling edge t sal 12 ns a-bus hold time after ale falling edge t hal 5ns rd x cs falling edge to d-bus valid t drd 020ns d-bus float after rd x cs rising edge t drdh 015ns rdxcs ale ad t wl t sal t hal t drdh t hlr t drd t hrl address data
delic timing diagrams preliminary data sheet 9-8 2003-08 in motorola mode, an interrupt acknowledge cycle consists of one iack pulse, during which the interrupt vector is issued by the delic. in intel/infineon mode, an interrupt acknowledge cycle consists of two iack pulses. note that the interrupt vector is issued as a response to the second pulse. the source of the vector is the oak mailbox interupt vector register (ivec). the dsp determines the value stored in this register by a write operation. ireq is not deactivated by the iack pulses directly, but by a p write access to obusy. figure 9-7 interrupt acknowledge cycle timing in motorola mode figure 9-8 interrupt acknowledge cycle timing in intel/infineon mode table 9-7 interrupt acknowledge cycle timing parameter symbol limit values unit test condition min. max. d-bus valid after iack falling edge t dadv 0 20 ns output load capacity of 50 pf d-bus float after iack rising edge t dadt 015ns iack pulse width t wa 25 ns interval between two ack pulses t ha 10 1) 1) valid only for intel/infineon mode. ns iack d t dadv t dadt vector iack d t dadv t dadt t wa t ha t wa vector
delic timing diagrams preliminary data sheet 9-9 2003-08 figure 9-9 ireq deactivation timing note: ireq is deactivated due to p write operation to obusy register. in motorola mode ds and cs together time the write access. in intel mode wr alone times the write access. for more details regarding the timing required during write access to the delic, refer to section 9.2. the other signals required for a write operation to obusy in each mode, are assumed to be driven. 9.4 dma access timing the exact behavior required from the p interface signals during a dma access depends on the following modes: motorola or intel mode: determined by the mode input pin. normal or ?fly-by? mode: programmable in the control register of the p interface. in any mode, the dack input is used to indicate that this is a dma transaction, and to select the dma mailbox. an activation via the cs signal is not required in such cases. 9.4.1 dma access timing in motorola mode in this mode ds is used for timing the access, while r/w is used to distinguish between dma read transactions and dma write transactions. the r/w input signal is used differently in normal mode and in fly-by mode. the next table shows how r/w should be used in each mode during dma transactions: table 9-8 r/w behavior during dma transactions in normal and fly-by mode mode r/w = ?0? r/w = ?1? normal (non-fly-by) write dma transaction. (a response to dma transmitter request) read dma transaction. (a response to dma receiver request) fly-by read dma transaction. (a response to dma receiver request) write dma transaction. (a response to dma transmitter request) dsxcs ireq t dwi wr
delic timing diagrams preliminary data sheet 9-10 2003-08 in fly-by mode r/w is used inverted to the normal mode, since the same signal, r/w , is required for concurrent accesses of an external memory device. table 9-9 dma transaction timing in mototrola mode parameter symbol limit values unit test conditions min. max. dack setup time to ds falling edge t sas 7 ns output load capacity of 50 pf dack hold time after ds rising edge t hsa 5ns d-bus setup time to ds rising edge t sds 5ns d-bus hold time after ds rising edge t hsd 10 ns dreqt/dreqr delay after ds falling edge t dsr 036ns r/w setup time to ds falling edge t srws 7ns r/w hold time after ds rising edge t hsrw 5ns ds pulse width and interval between ds pulses t ws 30 ns d-bus valid after ds falling edge t dsdv 022 d-bus float (high impedance) after ds rising edge t dsdt 015
delic timing diagrams preliminary data sheet 9-11 2003-08 figure 9-10 dma write transaction timing in motorola mode note: r/w is shown for normal mode. in fly-by mode, r/w should be high during dma write transactions. ds dack r/w d dreqt t sas t hsa t sds t hsd t dsr t srws t ws t hsrw last byte t ws
delic timing diagrams preliminary data sheet 9-12 2003-08 figure 9-11 dma read-transaction timing in motorola mode note: r/w is shown for normal mode. in fly-by mode, r/w should be low during dma read transactions. 9.4.2 dma access timing in intel/infineon mode in this mode, r and w are used for timing the access and to determine whether a dma read cycle or dma write cycle has occured. r and w input signals are used in opposite ways in normal mode and in fly-by mode. the next table shows how r and w should be used in each mode during dma transactions: ds dack r/w d dreqr t sas t hsa t dsr t srws t ws t hsrw t dsdv t dsdt last byte t ws
delic timing diagrams preliminary data sheet 9-13 2003-08 in fly-by mode r and w are used inverted to the normal mode, because these signals are required also for concurrent accesses of an external memory device. table 9-10 r/w behavior during dma transactions in normal and fly-by mode mode r = ?1?, w = ?0? r = ?0?, w = ?1? normal (non-fly-by) write dma transaction. (a response to dma transmitter request) read dma transaction. (a response to dma receiver request) fly-by read dma transaction. (a response to dma receiver request) write dma transaction. (a response to dma transmitter request) table 9-11 dma transaction timing in intel/infineon mode parameter symbol limit values unit test conditions min. max. dack setup time to w or r falling edge t saw t sar 7 ns output load capacity of 50 pf dack hold time after w or r rising edge t hwa t hra 5ns d-bus setup time to w rising edge t sdw 5ns d-bus hold time after w rising edge t hwd 10 ns dreqt/dreqr delay after w or r falling edge t dwr t drr 036ns w pulse width and interval between w pulses t ww 30 ns r pulse width and interval between r pulses t wr 30 ns d-bus valid after r falling edge t drdv 022 d-bus float (high impedance) after r rising edge t drdt 015
delic timing diagrams preliminary data sheet 9-14 2003-08 figure 9-12 dma write transaction timing in intel/infineon mode note: the figure shows a transaction in normal mode. in fly-by mode, rd is used during dma write transactions, instead of wr figure 9-13 dma read transaction timing in intel/infineon mode note: the figure shows a transaction in normal mode. in fly-by mode, wr is used during dma read-transactions, instead of rd . wr (rd ) dack d dreqt t saw t hwa t sdw t hwd t dwr t ww last byte t ww rd (wr ) dack d dreqr t sar t hra t drr t drdv t drdt last byte t wr t wr
delic timing diagrams preliminary data sheet 9-15 2003-08 9.5 iom ? -2 interface timing figure 9-14 iom ? -2 interface timing with single data rate dcl note: 1) t ddf = 0.5 t dcl + t ddc ? t fh table 9-12 timing characteristics of the iom ? -2 parameter symbol limit values unit conditions min. typ. max. frame sync. hold t fh 30 ns frame sync. setup t fs 70 ns frame sync. high t fwh 130 ns frame sync. low t fwl t dcl data delay to clock t ddc 100 ns data delay to frame 1) t ddf 150 ns data setup t ds 20 ns data hold t dh 50 ns
delic timing diagrams preliminary data sheet 9-16 2003-08 figure 9-15 timing of the iom ? -2 interface with double data rate dcl note: 1) t ddf = 0.5 t dcl + t ddc ? t fh table 9-13 timing characteristics of the iom ? -2 parameter symbol limit values unit conditions min. typ. max. frame sync hold t fh 30 ns frame sync setup t fs 70 ns frame sync high t fwh 130 ns frame sync low t fwl t dcl data delay to clock t ddc 100 ns data delay to frame 1) t ddf 150 ns data setup t ds 20 ns data hold t dh 50 ns
delic application hints preliminary data sheet 10-1 2003-08 10 application hints 10.1 delic connection to external microprocessors figure 10-1 delic connection to inte l 80386ex (demuxed configuration) a0 a(5..1) ad(7..0) dreqr dreqt dack d(7..0) csn wr rd intr drq0 drq1 ble a(5..1) 80386ex vcc 2.7v-3.6v,25mhz delphi ale cs wr rd ireq 80386ex.vsd dack0 dack1
delic application hints preliminary data sheet 10-2 2003-08 figure 10-2 delic connection to siem ens c165 (demuxed configuration) hold delic vcc 5v, 20mhz hlda a(5..0) ad(7..0) csn wr rd intn hold hlda 8237 drq0 drq1 dack0 dack1 hold hlda 8237 dreqr dack wr ireq rd ale cs d(7..0) a(5..0) dma controller c165.vsd infineon c165 dreqt
delic application hints preliminary data sheet 10-3 2003-08 10.2 delic worksheets figure 10-3 delic-lc pcm unit mode 0 ( 4 ports with 2 mbit/s) dsp pcmu data buffer 0xa000 0xa01f 0xa020 0xa03f 0xa040 0xa060 0xa05f 0xa07f 0xa080 0xa09f 0xa0a0 0xa0bf 0xa0c0 0xa0df 0xa0e0 0xa0ff in 0 in 1 in 2 in 3 out 0 out 1 out 2 out 3 txd0 txd1 txd2 txd3 rxd0 rxd1 rxd2 rxd3 tsc0 tsc1 tsc2 tsc3 0 15 pcr address: 0xd060 dr 00: 4 x 2.048 mbit/s 01: 2 x 4.096 mbit/s 10: 1 x 8.192 mbit/s 11: 1 x 16.384 mbit/s dc 0: single clock 1: double clock od 0: push pull mode 1: open drain mode a 0: pcmu is idle 1: pcmu is active icdb 0: frame buffer 0 accessed by the dsp 1: frame buffer 1 accessed by the dsp sfh 0: the first 128 time-slots are used 1: the second 128 time-slots are used 0 15 ptscr0 address: 0xd062 set and read 0xd063 reset and read 0 15 ptscr1 address: 0xd064 set and read 0xd065 reset and read 0 15 ptscr2 address: 0xd066 set and read 0xd067 reset and read 0 15 ptscr3 address: 0xd068 set and read 0xd069 reset and read 0 15 ptscr4 address: 0xd06a set and read 0xd06b reset and read 0 15 ptscr5 address: 0xd06c set and read 0xd06d reset and read 0 15 ptscr6 address: 0xd06e set and read 0xd06f reset and read 0 15 ptscr7 address: 0xd070 set and read 0xd071 reset and read 0 15 pdpr address: 0xd072 00000000
delic application hints preliminary data sheet 10-4 2003-08 figure 10-4 command/ indication handshake of general mailbox mgen 0xd143 (msb) 0xd142 (lsb) 0xd144 (all) 0x43 0x42 mdt0 mdt1 mdt2 mdt3 mdt4 mdt5 mdt6 mdt7 0xd100 0xd102 0xd104 0xd106 0xd108 0xd10a 0xd10c 0xd10e 0x07 0x06 0x09 0x08 0x0b 0x0a 0x01 0x00 0x03 0x02 0x0d 0x0c 0x0f 0x0e 0x05 0x04 mcmd ( p -> dsp) mbusy ( p <- dsp) 0xd141 (inh. bel.) bit 7 0xd140 (8 bit) 0x41 0x40 mdt8 mdt9 mdt10 mdt11 mdt12 mdt13 mdt14 mdt15 0xd110 0xd112 0xd114 0xd116 0xd118 0xd11a 0xd11c 0xd11e 0x17 0x16 0x19 0x18 0x1b 0x1a 0x11 0x10 0x13 0x12 0x1d 0x1c 0x1f 0x1e 0x15 0x14 p expanded mailbox p mailbox mailbox-synchr. p dsp ogen 0xd163 (msb) 0xd162 (lsb) 0xd164 (all) 0x63 0x62 odt0 odt1 odt2 odt3 odt4 odt5 odt6 odt7 0xd120 0xd122 0xd124 0xd126 0xd128 0xd12a 0xd12c 0xd12e 0x27 0x26 0x29 0x28 0x2b 0x2a 0x21 0x20 0x23 0x22 0x2d 0x2c 0x2f 0x2e 0x25 0x24 ocmd ( p <- dsp) obusy ( p -> dsp) 0xd161 (16 bit) bit 15 0x61 (8 bit) odt8 odt9 odt10 odt11 odt12 odt13 odt14 odt15 0xd130 0xd132 0xd134 0xd136 0xd138 0xd13a 0xd13c 0xd13e 0x37 0x36 0x39 0x38 0x3b 0x3a 0x31 0x30 0x33 0x32 0x3d 0x3c 0x3f 0x3e 0x35 0x34 dsp expanded mailbox dsp mailbox mailbox-synchr. p dsp 0xd160 (8 bit) (inh. bel.) 0x60
delic peb 20571 mailbox protocol description preliminary data sheet 11-1 2003-08 11 mailbox protocol description the following chapters describe the way of communication between delic and an external p via the mailbox. if no dma is used the general mailbox contains 32 data registers. if dma is used there are actually two different mailboxes. in this case the dma mailbox consists of 16 data registers and the general mailbox also contains 16 data registers. for more details especially initialization of the different units refer to the provided application notes. note: as a reference, elic registers with similar functionality are appended in brackets. 11.1 mailbox access 11.1.1 mailbox access transmit direction (p->delic) the general mailbox for transmit direction ( figure 11-1 ) consists of 20 (36) registers. one register (mcmd) contains the command to be processed by the delic. another register (mbusy) just consists of a busy bit indicating whether the mailbox is free to be written to or not. two other registers (mgen low and mgen high) serve for general parameters. a block of 16 (32) parameter registers contains data. writing to the command register sets the busy bit and thereby an interrupt in the delic. if the delic has processed the command it clears the busy bit to release the mailbox. 11.1.2 mailbox access receive direction (delic->p) the mailbox for receive direction ( figure 11-2 ) consists of 20 (36) registers. one register (ocmd) contains the indication to be processed by the p. another register (obusy) just consists of a busy bit which has to be cleared by the p after processing the indication in order to release the mailbox. two other registers (ogen low and ogen high) serve as general parameters. a block of 16 (32) parameter registers contains data associated with the indication.
delic peb 20571 mailbox protocol description preliminary data sheet 11-2 2003-08 figure 11-1 transmit mailbox structure mcmd mbusy mdt0 low mdt7 high delic lsb p mdt15/tdt7 high mdt8/tdt0 low mgen low mgen high bsy 0 0 0 0 0 0 0 0 7654321 0x40 0x41 0x00 0x0f 0x1f 0x10 0x42 0x43 deli_552.emf command general parameter 1 general parameter 2 parameter 1 parameter 16 parameter 17 parameter 32
delic peb 20571 mailbox protocol description preliminary data sheet 11-3 2003-08 figure 11-2 receive mailbox structure both sides, p and delic, use the same procedure to perform write accesses to the mailbox. if one side wants to put a message into the mailbox it has to check whether the mailbox is free. if the mailbox is free the parameters have to be written first than the command ( figure 11-3 ). p delic lsb ocmd obusy odt0 low odt7 high odt15/rdt7 high ogen low ogen high odt8/rdt0 low bsy 0 0 0 0 0 0 0 0x60 0x61 0x20 0x2f 0x3f 0x62 0x63 0x30 deli_551.emf indication general parameter 1 general parameter 2 parameter 1 parameter 16 parameter 17 parameter 32 76543210
delic peb 20571 mailbox protocol description preliminary data sheet 11-4 2003-08 figure 11-3 flow diagram: mailbox write access 11.2 subscriber address (sad) interpretation in this chapter sad is used commonly for the subscriber address. there are two possibilities to interpret sad 11.2.1 sad as iom-2 port and channel number the delic has two iom-2 ports. the subscriber address has to be interpreted as follows. bit76543210 sad3 sad2 sad1 sad0 sad3 iom-2 port number (2.048 mbit/s) 0 = iom-2 port 0 is addressed 1 = iom-2 port 1 is addressed sad2..0 iom-2 channel number (range: 0..7) (2.048 mbit/s) sad3..0 iom-2 channel number (range: 0..15) (4.096 mbit/s) is mailbox free (test obusy)? write command to mailbox (mcmd) yes no write parameters to mailbox (mdtx, mgen) deli_553.emf
delic peb 20571 mailbox protocol description preliminary data sheet 11-5 2003-08 11.2.2 sad as iom-2000 vip and channel number it is possible to connect up to 3 vips to the delic via the iom-2000 interface. each vip contains up to 8 channels. the subscriber address has to be interpreted as follows. 11.3 overview of commands and indications the following tables give an overview of all commands and indications according name, code value, parameters and the referring page where the detailed description can be found. 11.3.1 commands and indications for boot sequence bit76543210 sad4 sad3 sad2 sad1 sad0 sad4..3 vip number 00 = vip 0 is addressed 01 = vip 1 is addressed 10 = vip 2 is addressed 11 = reserved sad2..0 iom-2000 channel number (range: 0..7) table 11-1 boot commands name mcmd mdt0 mdt1..15 page start boot 0x55 11-13 write program memory 0xan n = amount start address data 11-13 write data memory 0xen n = amount start address data 11-14 finish boot 0x1f 11-13
delic peb 20571 mailbox protocol description preliminary data sheet 11-6 2003-08 11.3.2 general commands and indications table 11-2 boot indications name ocmd odt0 page start loading program ram 0x1f 11-15 start loading data ram 0xef 11-15 error 0b011100xx xxx=error code 11-15 firmware version indication 0x00 version number 11-15 table 11-3 general commands name ocmd ogen low ogen high odtx page write register 0x01 size mdt0: destination address mdtx: register value(s) 11-16 read register 0x02 size mdt0: start address for read 11-17 table 11-4 general indications name ocmd ogen low ogen high odtx page read register 0x01 size value(s) read from register 11-18
delic peb 20571 mailbox protocol description preliminary data sheet 11-7 2003-08 11.3.3 commands and indications for configuration table 11-5 configuration commands name mcmd mgen low mgen high mdtx page iom-2000 reference channel select 0x05 iom-2000 vip and channel no. 11-20 iom-2000 delay measurement 0x04 iom-2000 vip and channel no. 11-21 iom-2000 vip channel configuration 0x03 mdt0 h= ticcmr[31..24] mdt0 l= ticcmr[23..16] mdt1 h= ticcmr[15..8] mdt1 l= ticcmr[7..0] 11-22 ghdlc configuration 0x14 ghdlc no. mdt0 l = mode information mdt1 = normal address mdt2 = broadcast address 11-22 finish initialization 0x06 11-24 table 11-6 configuration indications name ocmd ogen low ogen high odtx page iom-2000 far- end code violation 0x07 size iom-2000 vip and channel no. fecv 11-24 iom-2000 delay 0x04 delay value 11-25 finish vip channel configuration 1) 1) this indication is only sent if the read bit of ticcmr has been set in iom-2000 vip channel configuration command 0x02 delay value odt0 h= ticstr[31..24] odt0 l= ticstr[23..16] odt1 h= ticstr[15..8] odt1 l= ticstr[7..0] 11-26
delic peb 20571 mailbox protocol description preliminary data sheet 11-8 2003-08 11.3.4 commands and indications for iom-2 c/i channels 11.3.5 commands and indications for iom-2 monitor channel table 11-7 iom-2 c/i command name mcmd mgen high mdtx page write c/i value 0x23 size iom-2 port and channel no. c/i value 11-27 table 11-8 iom-2 c/i indication name ocmd ogen high odtx page change detected 0x41 size iom-2 port and channel no. new c/i value 11-27 table 11-9 iom-2 monitor commands name mcmd mgen low mgen high mdtx page search on 0x2b 11-29 search reset 0x2c 11-30 monitor reset 0x2d 11-30 transmit continuous 0x29 iom-2 port and channel no. size data 11-30 transmit 0x28 iom-2 port and channel no. size data 11-30 transmit&receive/ receive only 0x2a iom-2 port and channel no. size data 11-30
delic peb 20571 mailbox protocol description preliminary data sheet 11-9 2003-08 11.3.6 commands and indications for iom-2000 c/i channels table 11-10 iom-2 monitor indications name ocmd ogen low ogen high odtx page transfer ready 0x53 11-31 receive continuous 0x52 size data 11-31 receive 0x51 size data 11-31 transmit abort 0x55 11-32 monitor active 0x54 iom-2 port and channel no. 11-32 table 11-11 iom-2000 c/i command name mcmd mgen high mdtx page write c/i value 0x0b size iom-2000 vip and channel no. c/i value 11-38 table 11-12 iom-2000 c/i indication name ocmd ogen high odtx page change detected 0x11 size iom-2000 vip and channel no. new c/i value 11-38
delic peb 20571 mailbox protocol description preliminary data sheet 11-10 2003-08 11.3.7 commands and indications for hdlc channel 11.3.8 commands and indications for ghdlc channel table 11-13 hdlc commands name mcmd mgen low mgen high mdtx page reset 0x1f size hdlc no. receiver or transmitter or both 11-40 transmit 0x1d hdlc no. size data 11-41 transmit continuous 0x1e hdlc no. size data 11-41 activation/ deactivation 0x20 size hdlc no. and activation information 11-41 table 11-14 hdlc indications name ocmd ogen low ogen high odtx page error 0x34 hdlc no. 0x01 odt0 l: error code 11-42 transmit ready 0x33 hdlc no. 11-43 receive 0x31 hdlc no. size data 11-44 receive continuous 0x32 hdlc no. size data 11-44 table 11-15 ghdlc commands name mcmd mgen low mgen high mdtx page reset 0x15 size ghdlc no. 11-46 transmit 0x11 ghdlc no. size data 11-47 transmit continuous 0x12 ghdlc no. size data 11-48
delic peb 20571 mailbox protocol description preliminary data sheet 11-11 2003-08 11.3.9 switching 11.4 boot procedure after reset the delic jumps into the boot routine and waits for downloading a program via the p-mailbox. figure 11-4 shows the handshake. table 11-16 ghdlc indications name ocmd ogen low ogen high odtx page error 0x24 ghdlc no. 0x01 odt0 l: error code 11-48 fatal error 0x25 ghdlc no. 0x02 odt0: status word 11-48 transmit ready 0x23 ghdlc no. 11-49 receive 0x21 ghdlc no. size data 11-49 receive continuous 0x22 ghdlc no. size data 11-49 table 11-17 switching commands name mcmd mgen high mdtx page connect 0x17 size connection identifier source/destination interface type source time slot no. destination time slot no. 11-50 disconnect 0x18 size connection identifier 11-52
delic peb 20571 mailbox protocol description preliminary data sheet 11-12 2003-08 figure 11-4 boot sequence the range for amount must be between 1 and 15. in case of an verification failure or if an amount of zero has been used the start boot command has to be issued again before continuing the download. after issuing start boot any invalid command is ignored. start boot p delic write program memory [amount, address, data] finish boot start loading program ram write program memory [amount, address, data] write program memory [amount, address, data] start boot write data memory [amount, address, data] finish boot start loading data ram write data memory [amount, address, data] write data memory [amount, address, data] deli_554.emf firmware version
delic peb 20571 mailbox protocol description preliminary data sheet 11-13 2003-08 11.4.1 boot commands after reset the delic waits for downloading a program from the processor via the mailbox indicated by the start loading program ram indication (0x1f) ( figure 11-4 ). 11.4.1.1 start boot command (0x55) this command has to be issued before using the write program memory command (0xan) and write data memory command (0xen) directly after receiving the start loading program ram indication (0x1f) or the start loading data ram indication (0xef). mailbox register (mcmd) p-write address: 40 h 11.4.1.2 finish boot command (0x1f) first usage of this command finishes filling of the program memory. the second usage finishes filling of the data memory and let the delic wait for initialization commands. mailbox register (mcmd) p-write address: 40 h 11.4.1.3 write program memory command (0xan) after issuing the start boot command (0x55) the first time the program memory can be filled with this command. the filling has to be finished with the finish boot command (0x1f). mailbox register (mcmd) p-write address: 40 h bit76543210 01010101 bit76543210 00011111 bit76543210 1 0 1 0 n3n2n1n0 n3..0 amount of 16-bit data words within mdt1 to mdt15 (range: 1..15)
delic peb 20571 mailbox protocol description preliminary data sheet 11-14 2003-08 mailbox register (mdt0) p-write address: 00+01 h 11.4.1.4 write data memory command (0xen) after issuing the start boot command (0x55) the second time the data memory can be filled with this command. the filling has to be finished with the finish boot command (0x1f). mailbox register (mcmd) p-write address: 40 h mailbox register (mdt0) p-write address: 00+01 h bit76543210 high ad(15:8) bit76543210 low ad(7:0) ad15..0 start address (delic address space) bit76543210 1 1 1 0 n3n2n1n0 n3..0 amount of 16-bit data words within mdt1 to mdt15 (range: 1..15) bit76543210 high ad(15:8) bit76543210 low ad(7:0) ad15..0 start address (delic address space)
delic peb 20571 mailbox protocol description preliminary data sheet 11-15 2003-08 11.4.2 boot indications 11.4.2.1 error indication (0b011100xx) mailbox register (ocmd) p-read address: 60 h 11.4.2.2 start loading program ram indication (0x1f) this indication is issued after reset to inform the processor that program download can begin. mailbox register (ocmd) p-read address: 60 h 11.4.2.3 start loading data ram indication (0xef) this indication is issued after issuing the finish boot command (0x1f) the first time to inform the processor that data download can begin. mailbox register (ocmd) p-read address: 60 h 11.4.2.4 firmware version indication (0x00) this indication is sent after the last finish boot command (0x1f) to confirm the correct program and daa boot. bit76543210 011100en1en0 en1..0 error code 00 = wrong command error 01 = data verification failure 10 = incorrect amount of data (zero size) note: after an zero size error and after a verification failure the start boot command (0x55) has to be issued again. bit76543210 00011111 bit76543210 11101111
delic peb 20571 mailbox protocol description preliminary data sheet 11-16 2003-08 mailbox register (odt0) p-read address: 20+21 h 11.5 general commands and indications the following commands and indications are used during initialization and during normal operation. 11.5.1 general commands 11.5.1.1 write register command (0x01) the command writes any 16-bit value(s) to delic?s register(s), starting from the specified destination address (and continuing to the consecutive address(es)). parameter: ? number of values to be written ? destination address for write ? register value(s) to be written mailbox register (mgen low) p-write address: 42 h bit76543210 high fvno(15:8) bit76543210 low fvno(7:0) fvno15..0 firmware version number bit76543210 (size3) size2 size1 size0 size3..0 number of valid 16-bit values within mdt1..7(15) (range: 1..7(15))
delic peb 20571 mailbox protocol description preliminary data sheet 11-17 2003-08 mailbox register (mdt0) p-write address: 00+01 h mailbox register (mdt1..7(15)) p-write 11.5.1.2 read register command (0x02) the command initiates read access(es) to delic?s register(s), starting from the specified base address (and continuing to the consecutive address(es)). bit76543210 high dad(15:8) bit76543210 low dad(7:0) dad15..0 destination address (delic address space) bit76543210 high wrv(15:8) bit76543210 low wrv(7:0) wrv15..0 mdt1: write value to destination address dad mdt2: write value to destination address dad+1 .. mdt7(15): write value to destination address dad+6(14)
delic peb 20571 mailbox protocol description preliminary data sheet 11-18 2003-08 parameter: ? number of values to be read ? base address for read mailbox register (mgen low) p-write address: 42 h mailbox register (mdt0) p-write address: 00+01 h 11.5.2 general indication 11.5.2.1 read register indication (0x01) the indication returns the values read from delic?s register(s) as specified in the read register command (0x02). bit76543210 (size4) size3 size2 size1 size0 size4..0 amount of 16-bit values to be read from the base address (range: 1..8(16)) bit76543210 high bad(15:8) bit76543210 low bad(7:0) bad15..0 base address from which register value is to be read
delic peb 20571 mailbox protocol description preliminary data sheet 11-19 2003-08 parameter: ? number of read values ? read register values mailbox register (ogen low) p-read address: 62 h mailbox register (odt0..7(14)) p-read 11.6 initialization/configuration after issuing the last finish boot command (0x1f) the delic waits for the finish initialization command (0x06) before it starts all tasks. here the device can be configured according the application requirements. bit151413121110 9 8 (size4) size3 size2 size1 size0 size4..0 number of valid 16-bit values that have been read (range: 1..8(16)) bit76543210 high rrv(15:8) bit76543210 low rrv(7:0) rrv15..0 odt0: read register value from base address bad odt1: read register value from base address bad+1 .. odt7(15): read register value from base address bad+7(15)
delic peb 20571 mailbox protocol description preliminary data sheet 11-20 2003-08 figure 11-5 initialization flow diagram: configuration example 11.6.1 configuration commands 11.6.1.1 iom-2000 reference channel select command (0x05) the command selects the vip channel which provides the reference clock. parameter: ? iom-2000 vip and channel number ? external reference source finish boot p delic any configuration command read register [amount, address] any configuration command write register [amount, address, data] finish initialization read register [amount, data] iom-2000 vip channel configuration finish vip channel configuration deli_550.emf
delic peb 20571 mailbox protocol description preliminary data sheet 11-21 2003-08 mailbox register (mgen low) p-write address: 42 h note: this command is only applicable for channels in lt-t mode 11.6.1.2 iom-2000 delay measurement command (0x04) this command selects the vip channel in which the line delay is to be measured. the delay is reported with the iom-2000 delay indication (0x04). parameter: ? iom-2000 vip and channel number mailbox register (mgen low) p-write address: 42 h note: this command is only applicable for channels in u pn mode bit76543210 exref sad4 sad3 sad2 sad1 sad0 sad4..0 subscriber address i.e. iom-2000 vip and channel number exref external reference clock selection (lt-t) 0 = no external reference clock source. reference clock is generated from internal vip_n channel specified in refclk(2:0) and passed on via refclk pin to vip_n-1 or directly to delic. 1 = reference clock is generated from external source via pin inclk and passed on via refclk pin to vip_n-1 or directly to delic. the internal reference clock generation logic is disabled. note: vip_0 has the highest priority in terms of clock selection bit76543210 sad4 sad3 sad2 sad1 sad0 sad4..0 subscriber address i.e. iom-2000 vip and channel number
delic peb 20571 mailbox protocol description preliminary data sheet 11-22 2003-08 11.6.1.3 iom-2000 vip channel configuration command (0x03) the command initializes or re configures the channel register in the transiu for the specified vip channel. parameter: ? initialization values of vip channel command register ticcr (4 bytes including vip and channel number) mailbox register (mdt0 high) p-write address: 01 h mailbox register (mdt0 low) p-write address: 00 h mailbox register (mdt1 high) p-write address: 03 h mailbox register (mdt1 low) p-write address: 02 h note: for the meaning of the bits, refer to "transiu initialization channel command register" on page 6-15. ?x?=unused 11.6.1.4 ghdlc configuration command (0x14) mailbox register (mgen low) p-write address: 42 h bit151413121110 9 8 x vipadr(1:0) chadr(2:0) fil exlp bit76543210 plls pd dhen x x pdown loop tx_en bit151413121110 9 8 pllint aac(1:0) bbc(1:0) owin(2:0) bit76543210 mf_en mode(2:0) mosel(1:0) rd wr bit76543210 gca1 gca0 gca1..0 ghdlc channel address 00 = ghdlc channel 0 (all other combinations are reserved)
delic peb 20571 mailbox protocol description preliminary data sheet 11-23 2003-08 mailbox register (mdt0 low) p-write address: 00 h mailbox register (mdt1) p-write address: 02+03 h bit76543210 adm auto auto auto mode enable 0 = disable auto mode 1 = enable auto mode adm address mode 0 = 8-bit address mode 1 = 16-bit address mode bit76543210 high aad(15:8) bit76543210 low aad(7:0) aad15..0 address for address recognition (elic reg. ral1 and rah1) note: if adm is set to 0 (8-bit address) only the low part is considered
delic peb 20571 mailbox protocol description preliminary data sheet 11-24 2003-08 mailbox register (mdt2) p-write address: 04+05 h 11.6.1.5 finish initialization command (0x06) this command has to be issued after downloading program and data and configuring the delic correctly. it forces the delic to start with all tasks. mailbox register (mcmd) p-write address: 40 h 11.6.2 configuration indications 11.6.2.1 iom-2000 far-end code violation indication (0x07) this indication reports a far-end code violation (fecv) in the specified vip channel. parameter: ? iom-2000 vip and channel number mailbox register (ogen high) p-read address: 63 h bit76543210 high bad(15:8) bit76543210 low bad(7:0) bad15..0 broadcast address (elic reg. ral2 and rah2) note: if adm is set to 0 (8-bit address) only the low part is considered bit76543210 00000110 bit76543210 (size5) size4 size3 size2 size1 size0 size5..0 amount of entries in odt0..7(15) (range: 1..16(32))
delic peb 20571 mailbox protocol description preliminary data sheet 11-25 2003-08 for every entry (one byte per entry): mailbox register (odt0..7(15)) p-read 11.6.2.2 iom-2000 delay indication (0x04) this indication returns the measured line delay value of an u pn channel. this indication is the answer to the iom-2000 delay measurement command (0x04). parameter: ? iom-2000 vip and channel number ? delay value mailbox register (ogen high) p-read address: 63 h mailbox register (ogen low) p-read address: 62 h note: this command is only applicable for channels in u pn mode bit76543210 fecv sad4 sad3 sad2 sad1 sad0 sad4..0 subscriber address i.e. iom-2000 vip and channel number fecv far-end code violation 0 = no far-end code violation detected 1 = far-end code violation (bit error) detected bit151413121110 9 8 sad4 sad3 sad2 sad1 sad0 sad4..0 subscriber address i.e. iom-2000 vip and channel number bit76543210 dv7 dv6 dv5 dv4 dv3 dv2 dv1 dv0 dv7..0 delay value
delic peb 20571 mailbox protocol description preliminary data sheet 11-26 2003-08 11.6.2.3 finish vip channel configuration indication (0x02) after issuing the iom-2000 vip channel configuration command (0x03) with set read bit the delic confirms the command by this indication. mailbox register (odt0 high) p-read address: 21 h mailbox register (odt0 low) p-read address: 20 h mailbox register (odt1 high) p-read address: 23 h mailbox register (odt1 low) p-read address: 22 h note: for the meaning of the bits, refer to "transiu initialization channel status register (ticstr)" on page 6-20. ?x?=unused 11.7 iom-2 c/i handling purpose of the c/i handler is to transmit c/i values and to receive c/i value changes on the c/i channels. the c/i values itself are not interpreted. a new c/i value will be considered if it is detected for at least two consecutive frames (double last look). the delic considers all channels affected by at least one c/i value change. after detecting the first change the delic reports it to the p. as soon as the mailbox is free the delic sends the current c/i values of the affected channels, together with their addresses, to the p. if the p is fast enough to serve the interrupts every change will be reported. but if the p is not as fast preceding changes according to the same channel will be lost ( figure 11-6 ). bit151413121110 9 8 x vipadr(1:0) chadr(2:0) fil exlp bit76543210 plls pd dhen x x pdown loop tx_en bit151413121110 9 8 pllint aac(1:0) bbc(1:0) owin(2:0) bit76543210 mf_en mode(2:0) mosel(1:0) rd wr
delic peb 20571 mailbox protocol description preliminary data sheet 11-27 2003-08 11.7.1 iom-2 c/i command the following command is sent from the p to the delic. 11.7.1.1 write c/i value command (0x23) (elic reg.: macr, madr, maar) this command provides the delic with new c/i values to be sent on the specified channels. it can be issued any time. parameter: ? amount of following entries for every entry: ? iom-2 port and channel number ? c/i value see "common mailbox parameter structure" on page 11-27 11.7.2 iom-2 c/i indication the following indication is sent from the delic to the p. 11.7.2.1 change detected indication (0x41) if at least one change is detected this indication will be issued. the amount of entries depends on the mailbox size and the amount of used iom-2 channels. maximum values of 8 entries (if dma is used) or 16 (if dma is not used) are possible. parameter: ? amount of following entries for every entry: ? iom-2 port and channel number ? c/i value see "common mailbox parameter structure" on page 11-27 11.7.3 common mailbox parameter structure both command and indication have the same structure.
delic peb 20571 mailbox protocol description preliminary data sheet 11-28 2003-08 mailbox register (mgen high) p-write address: 43 h mailbox register (ogen high) p-read address: 63 h for every entry (two bytes per entry): mailbox register (mdt0..7(15) low) p-write mailbox register (odt0..7(15) low) p-read mailbox register (mdt0..7(15) high) p-write mailbox register (odt0..7(15) high) p-read 11.7.4 flow diagram the following diagram describes the way of handling c/i value changes. it is assumed that the mailbox is not free as the first change was detected. after releasing the mailbox by the p the delic sends the c/i values and their iom-2 channel addresses. the preceding change on channel 6 will not be reported. bit76543210 (size4) size3 size2 size1 size0 size4..0 amount of valid entries in mdt0..7(15) or odt0..7(15) (range: 1..8(16)) bit76543210 sad3 sad2 sad1 sad0 sad3..0 subscriber address i.e. iom-2 port and channel number bit76543210 ci5ci4ci3ci2ci1ci0 ci5..0 6-bit c/i value ci3..0 4-bit c/i value
delic peb 20571 mailbox protocol description preliminary data sheet 11-29 2003-08 figure 11-6 c/i flow diagram: receiving c/i value changes 11.8 iom-2 monitor handling according to the monitor channels the delic has to manage the data exchange between iomu and mailbox. only one of all possible channels is served at the same time. the main task of the delic is to transform an acknowledged block stream from and to the mailbox to an acknowledged byte stream from and to the iomu. if the p issues a command it has to wait for the related indication before the next command can be issued. 11.8.1 iom-2 monitor commands the following commands are sent from the p to the delic: 11.8.1.1 search on command (0x2b) (elic bit: mfso) by this command the delic is instructed to search for an active monitor channel. after finding an active channel the search mechanism is stopped and the event is reported with monitor active indication. this command can be issued any time. if there is a transmission command in progress the search mode is started after transmission was terminated. delic iom-2 deli_555.emf 1st c/i value change [ch3] 2nd c/i value change [ch6] (n-1)th c/i value change [ch2] nth c/i value change [ch6] p change detected indication [n, channel + value..] release mailbox
delic peb 20571 mailbox protocol description preliminary data sheet 11-30 2003-08 11.8.1.2 search reset command (0x2c) (elic bit: omso) by this command the search mode is stopped. this command can be issued any time. it will not stop a running transmission. 11.8.1.3 monitor reset command (0x2d) (elic bit: mffr) by this command the execution of the current transfer command is stopped immediately. 11.8.1.4 transmit continuous command (0x29) (elic bits: mft1..0) this command starts transmission of one of more blocks. the search mode is suspended until transmission was terminated. after acknowledging the last sent byte transfer ready is issued to ask for a new block. the size of the blocks is variable. the last block is sent with transmit or transmit & receive. only with the first appearance of this command the first parameter will be considered. parameter: ? iom-2 port and channel number ? size of data block ? data block see "common mailbox parameter structure" on page 11-32 11.8.1.5 transmit command (0x28) (elic bits: mft1..0) this command starts transmission of a single/last block. the search mode is suspended until transmission was terminated. after transmission was completed (rising edge of mr) transfer ready is issued. if this command follows after transmit continuous the first parameter will be ignored. parameter: ? iom-2 port and channel number ? size of data block ? data block see "common mailbox parameter structure" on page 11-32 11.8.1.6 transmit&receive/receive only command (0x2a) (elic bits: mft1..0) this command starts transmission of a single/last block and waits for reception on the same channel. the search mode is suspended during transmission and reception. if this
delic peb 20571 mailbox protocol description preliminary data sheet 11-31 2003-08 command follows after transmit continuous the first parameter will be ignored. received blocks are reported with receive and/or receive continuous. if size of data is zero the command has the meaning of receive only i.e. reception on the specified channel is activated. parameter: ? iom-2 port and channel number ? size of data block ? data block see "common mailbox parameter structure" on page 11-32 11.8.2 iom-2 monitor indications the following indications are sent from the delic to the p. 11.8.2.1 transfer ready indication (0x53) (elic bit: mffi) indicates end of transmit or end of transmit broadcast or asks for a new block after transmit continuous. 11.8.2.2 receive continuous indication (0x52) (elic bit: mffi) this indication reports one of more received blocks to the p. the reception has not been terminated yet. parameter: ? size of data block ? data block mailbox register (ogen high) p-read address: 63 h 11.8.2.3 receive indication (0x51) (elic bits: mffi, mffe) the only/last received block is reported to the p. bit76543210 (size5) size4 size3 size2 size1 size0 size5..0 amount of following data bytes within odt0..7(15) (range: 1..16(32))
delic peb 20571 mailbox protocol description preliminary data sheet 11-32 2003-08 parameter: ? size of data block ? data block mailbox register (ogen high) p-read address: 63 h 11.8.2.4 transmit abort indication (0x55) (elic bit: mfab) the remote receiver aborted reception of a locally issued transmit command. 11.8.2.5 monitor active indication (0x54) (elic bit: mac) informs the p that an active monitor channel has been found. the p may issues receive only to activate the receiver. parameter: ? iom-2 port and channel number mailbox register (ogen low) p-read address: 62 h reset value: unchanged 11.8.3 common mailbox parameter structure this structure is valid for transmit continuous command (0x29), transmit command (0x28), transmit&receive/receive only command (0x2a). bit76543210 (size5) size4 size3 size2 size1 size0 size5..0 amount of following data bytes within odt0..7(15) (range: 1..16(32)) bit76543210 sad3 sad2 sad1 sad0 sad3..0 subscriber address i.e. iom-2 port and channel number (up to 16 channels)
delic peb 20571 mailbox protocol description preliminary data sheet 11-33 2003-08 mailbox register (mgen low) p-write address: 42 h mailbox register (mgen high) p-write address: 43 h 11.8.4 flow diagrams the following flow diagrams describe the way the delic transforms the protocols. n and m are always less or equal the mailbox size and less or equal the buffer size. figure 11-7 monitor flow diagram: transmit bit76543210 sad3 sad2 sad1 sad0 sad3..0 subscriber address i.e. iom-2 port and channel number (up to 16 channels) bit76543210 (size5) size4 size3 size2 size1 size0 size5..0 amount of following data bytes within mdt0..7(15) (range: 1..16(32)) transmit [ch, n bytes] 1st byte ack n th byte ack eom eom ack transfer ready p delic iom-2 [ch] deli_559.emf
delic peb 20571 mailbox protocol description preliminary data sheet 11-34 2003-08 figure 11-8 monitor flow diagram: transmit continuous transmit continuous [ch, n bytes] 1st byte 1st block ack n th byte 1st block ack eom eom ack transfer ready p delic iom-2 [ch] transmit [m bytes] transfer ready 1st byte last block ack m th byte last block ack deli_560.emf
delic peb 20571 mailbox protocol description preliminary data sheet 11-35 2003-08 figure 11-9 monitor flow diagram: search mode delic iom-2 [ch] p search on receive [n bytes] receive only [ch] monitor active [ch] 1st byte ack n th byte ack eom eom ack 1st byte deli_563.emf
delic peb 20571 mailbox protocol description preliminary data sheet 11-36 2003-08 figure 11-10 monitor flow diagram: receive only with receive continuous delic iom-2 [ch] p receive only [ch] receive [last bytes] receive continuous [16 (32) bytes] eom eom ack 1st byte ack 16 th (32 th) byte ack last byte ack 17 th (33 th) byte ack 17 th (33 th) byte deli_562.emf
delic peb 20571 mailbox protocol description preliminary data sheet 11-37 2003-08 figure 11-11 monitor flow diagram: transmit & receive 11.9 iom-2000 c/i handling the layer 1 state machine is accessed the same way as the c/i channels. 11.9.1 iom-2000 c/i command the following command is sent from the p to the delic: transmit & receive [ch, n bytes] receive [m bytes] p delic iom-2 [ch] 1st byte ack n th byte ack eom eom ack 1st byte ack m th byte ack eom eom ack deli_561.emf
delic peb 20571 mailbox protocol description preliminary data sheet 11-38 2003-08 11.9.1.1 write c/i value command (0x0b) this command provides the delic with new c/i values to be sent on the specified channels. it can be issued any time. parameter: ? amount of following entries for every entry: ? iom-2000 vip and channel number ? c/i value see "common mailbox parameter structure" on page 11-38 11.9.2 iom-2000 c/i indication the following indication is sent from the delic to the p. 11.9.2.1 change detected indication (0x11) if at least one change is detected this indication will be issued. the amount of entries depends on the mailbox size and the amount of used iom-2000 channels. maximum values of 8 entries (if dma is used) or 16 (if dma is not used) are possible. parameter: ? amount of following entries for every entry: ? iom-2000 vip and channel number ? c/i value see "common mailbox parameter structure" on page 11-38 11.9.3 common mailbox parameter structure both command and indication use the same structure. mailbox register (mgen high) p-write address: 43 h mailbox register (ogen high) p-read address: 63 h bit76543210 (size4) size3 size2 size1 size0 size4..0 amount of valid entries in mdt0..7(15) or odt0..7(15) (range: 1..8(16))
delic peb 20571 mailbox protocol description preliminary data sheet 11-39 2003-08 for every entry (two bytes per entry): mailbox register (mdt0..7(15) low) p-write mailbox register (odt0..7(15) low) p-read mailbox register (mdt0..7(15) high) p-write mailbox register (odt0..7(15) high) p-read 11.10 hdlc handling figure 11-12 hdlc frame structure 11.10.1 hdlc commands the following commands are sent from the p to the delic. bit76543210 sad4 sad3 sad2 sad1 sad0 sad4..0 subscriber address i.e. iom-2000 vip and channel number bit76543210 ci3ci2ci1ci0 ci3..0 c/i value flag address control crc flag field i- auto mode non-auto mode transparent mode 1 transparent mode 0 extended transparent mode device user deli_556.emf
delic peb 20571 mailbox protocol description preliminary data sheet 11-40 2003-08 11.10.1.1 reset command (0x1f) this command resets the specified hdlc controllers. parameter: ? amount of following entries for every entry: ? hdlc channel address ? receiver or transmitter or both mailbox register (mgen high) p-write address: 43 h for every entry (two bytes per entry): mailbox register (mdt0..7(15) low) p-write mailbox register (mdt0..7(15) high) p-write bit76543210 (size4) size3 size2 size1 size0 size4..0 amount of following entries within mdt0..7(15) (range: 1..8(12)) bit76543210 hca4 hca3 hca2 hca1 hca0 hca4..0 hdlc channel address bit76543210 rx tx tx transmitter will be reset (elic bit xres) 0 = no action 1 = reset rx receiver will be reset (elic bit rhr) 0 = no action 1 = reset
delic peb 20571 mailbox protocol description preliminary data sheet 11-41 2003-08 11.10.1.2 transmit command (0x1d) (elic bits: xtf, xme) this command initiates sending of a single message or the last block of a long message. after transmission transmit ready will be issued. parameter: ? hdlc channel address ? amount of data bytes ? data bytes see "common mailbox parameter structure" on page 11-44 11.10.1.3 transmit continuous command (0x1e) (elic bit: xtf) this command allows sending of one of more blocks. the last block has to be sent with the transmit command. the next block is requested by transmit ready indication. parameter: ? hdlc channel address ? amount of data bytes ? data bytes see "common mailbox parameter structure" on page 11-44 11.10.1.4 activation/deactivation command (0x20) (elic bit: rac) the command activates or deactivates the specified hdlc channel. parameter: ? amount of following entries for every entry: ? hdlc channel address mailbox register (mgen high) p-write address: 43 h bit76543210 (size5) size4 size3 size2 size1 size0 size5..0 amount of following bytes within mdt0..7(15) (range: 1..16(32))
delic peb 20571 mailbox protocol description preliminary data sheet 11-42 2003-08 for every entry (one byte per entry): mailbox register (mdt0..7(15)) p-write 11.10.2 hdlc indications the following indications are sent from the delic to the p. 11.10.2.1 error indication (0x34) this indication reports hdlc errors to the p. parameter: ? hdlc channel address ? error code according to the receiver following errors can occur: abort, crc-check failure, byte not complete, address recognition error, receive buffer overflow, extended hdlc frame (i.e. neither a rr nor an i frame in auto mode). according to the transmitter following errors can occur: underflow of the transmit buffer, repeat request according to long messages (long frame polled twice, collision after first block). mailbox register (ogen low) p-read address: 62 h bit76543210 d hca4 hca3 hca2 hca1 hca0 hca4..0 hdlc channel address d activation/deactivation bit 0 = activate hdlc channel 1 = deactivate hdlc channel note: both receiver and transmitter are activated/deactivated bit76543210 hca4 hca3 hca2 hca1 hca0 hca4..0 hdlc channel address
delic peb 20571 mailbox protocol description preliminary data sheet 11-43 2003-08 mailbox register (odt0 low) p-read address: 20 h 11.10.2.2 transmit ready indication (0x33) (elic bit xpr) this indication informs the p which hdlc controller finished the last transmit command. parameter: ? hdlc channel address mailbox register (ogen low) p-read address: 62 h bit76543210 txe2 txe1 txe0 rxe2 rxe1 rxe0 rxe2..0 receiver error codes 001 = abort (elic bits vfr, rab) 010 = crc check failure (elic bit crc) 011 = non octet (elic bit vfr) 100 = address recognition error (elic bits ha1..0) 101 = frame too short (elic bit vfr) 110 = receive buffer overflow (elic bits rfo, rdo) 111 = extended hdlc frame (auto mode: neither rr nor i frame) (elic bit ehc) txe2..0 transmitter error codes 001 = transmit buffer underflow (elic bits xdu, exe) 010 = repeat request (elic bit xmr) 011 = transmit buffer overflow 100 = collision detected bit76543210 hca4 hca3 hca2 hca1 hca0 hca4..0 hdlc channel address
delic peb 20571 mailbox protocol description preliminary data sheet 11-44 2003-08 11.10.2.3 receive indication (0x31) (elic bit rme) this indication reports a single or the last received block to the p. parameter: ? hdlc channel address ? amount of data bytes ? data bytes see "common mailbox parameter structure" on page 11-44 11.10.2.4 receive continuous indication (0x32) (elic bit rpf) this indication sends a received block to the p. more data follows. the last block will be sent with receive indication. parameter: ? hdlc channel address ? amount of data bytes ? data bytes see "common mailbox parameter structure" on page 11-44 11.10.3 common mailbox parameter structure the following structure is valid for following commands or indications respectively: transmit command (0x1d), transmit continuous command (0x1e), receive indication (0x31), receive continuous indication (0x32). mailbox register (mgen low) p-write address: 42 h mailbox register (ogen low) p-read address: 62 h bit76543210 hca4 hca3 hca2 hca1 hca0 hca4..0 hdlc channel address
delic peb 20571 mailbox protocol description preliminary data sheet 11-45 2003-08 mailbox register (mgen high) p-write address: 43 h mailbox register (ogen high) p-read address: 63 h 11.10.4 flow diagrams figure 11-13 hdlc flow diagram: transmit figure 11-14 hdlc flow diagram: transmit continuous bit76543210 (size5) size4 size3 size2 size1 size0 size5..0 amount of following data bytes within mdt0..7(15) or odt0..7(15) note: a size value of ?0? stands for a byte count of zero data bytes. thus the width of size is 5 bits to include a mailbox transfer of 16 data bytes, or 6 bits to include a mailbox transfer of 32 data bytes. transmit [ch, n bytes] h d l c f r a m e transfer ready [ch] p delic b/d [ch] deli_557.emf transmit continuous [ch, n bytes] h d l c f r a m e transfer ready [ch] p delic b/d [ch] transmit [ch, m bytes] transfer ready [ch] deli_558.emf transmit continuous [ch, n bytes] transfer ready [ch]
delic peb 20571 mailbox protocol description preliminary data sheet 11-46 2003-08 11.11 ghdlc handling according to the commands and indications the same parameter structure as in hdlc handling is used. the only difference is that hca4..0 (hdlc channel address) is called gca1..0 (ghdlc channel address). 11.11.1 ghdlc commands 11.11.1.1 reset command (0x15) this command resets the specified ghdlc channel. parameter: ? amount of following entries for every entry: ? ghdlc channel address mailbox register (mgen high) p-write address: 43 h for every entry (one byte per entry): mailbox register (mdt0 and mdt1) p-write bit76543210 size1 size0 size1..0 amount of following bytes within mdt0..7(15) bit76543210 gca1 gca0 gca1..0 ghdlc channel address
delic peb 20571 mailbox protocol description preliminary data sheet 11-47 2003-08 11.11.1.2 transmit command (0x11) parameter: ? ghdlc channel address ? transmit prepared or direct data ? enable/disable auto repeat ? amount of data bytes ? data bytes mailbox register (mgen low) p-write address: 42 h mailbox register (mgen high) p-write address: 43 h bit76543210 xpd/ xdd arep gca1 gca0 xpd/xdd transmit prepared or direct data (auto mode only) 0 = transmit direct data 1 = transmit prepared data arep auto repeat enable 0 = disable auto repeat 1 = enable auto repeat gca1..0 ghdlc channel address 00= ghdlc channel 0 (all other combinations are reserved) bit76543210 (size5) size4 size3 size2 size1 size0 size5..0 amount of data bytes within mdt0..7(15) (range: 1..16(32))
delic peb 20571 mailbox protocol description preliminary data sheet 11-48 2003-08 11.11.1.3 transmit continuous command (0x12) parameter: ? ghdlc channel address ? amount of data bytes ? data bytes mailbox register (mgen low) p-write address: 42 h mailbox register (mgen high) p-write address: 43 h 11.11.2 ghdlc indications 11.11.2.1 error indication (0x24) for the structure see "error indication (0x34)" on page 11-42 and replace hca4..0 (hdlc channel address) with gca1..0 (ghdlc channel address). 11.11.2.2 fatal error indication (0x25) this indication reports the status of the ghdlc unit to the p in case of an error. parameter: ? ghdlc channel address ? status of ghdlc channel bit76543210 gca1 gca0 gca1..0 ghdlc channel address 00= ghdlc channel 0 (all other combinations are reserved) bit76543210 (size5) size4 size3 size2 size1 size0 size5..0 amount of data bytes within mdt0..7(15) (range: 1..16(32))
delic peb 20571 mailbox protocol description preliminary data sheet 11-49 2003-08 mailbox register (ogen low) p-read address: 62 h mailbox register (odt0 high) p-read address: 21 h mailbox register (odt0 low) p-read address: 20 h note: for the meaning of the bits, refer to "ghdlc receive channel status registers 0..3" on page 6-40 11.11.2.3 transmit ready indication (0x23) for the structure see "transmit ready indication (0x33)" on page 11-43 and replace hca4..0 (hdlc channel address) with gca1..0 (ghdlc channel address). 11.11.2.4 receive indication (0x21) for the structure see "receive indication (0x31)" on page 11-44 and replace hca4..0 (hdlc channel address) with gca1..0 (ghdlc channel address). 11.11.2.5 receive continuous indication (0x22) for the structure see "receive continuous indication (0x32)" on page 11-44 and replace hca4..0 (hdlc channel address) with gca1..0 (ghdlc channel address). bit76543210 gca1 gca0 gca2..0 ghdlc channel address bit76543210 xxxxxxcolldunder bit76543210 empty over full rbfill(4:0)
delic peb 20571 mailbox protocol description preliminary data sheet 11-50 2003-08 11.12 b-channel switching (elic registers maar, madr, macr) purpose of the switching task is to manage connections between time slots i.e. to transfer data between memory locations. to every connection an identification is assigned in order to make fast disconnection possible and to avoid hole handling within the used connection table. the connection information can be read back with the "read register command (0x02)" on page 11-17. the internal connection table (base address t.b.d.) contains consecutive entries consisting of two consecutive 16-bit values each determining the source (first word) and destination (second word) time slot address. the actual time slot can be recalculated with the following table. 11.12.1 switching commands the following commands are sent from the p to the delic: 11.12.1.1 8-bit connect command (0x17) this command creates or overwrites a connection between two time slots. parameter: ? amount of following entries for every entry: ? connection identifier ? source unit ? source ts ? destination unit ? destination ts table 11-18 time slot address ranges unit direction address range time slot range iom-2 receive transmit 0x8000..0x803f 0x8040..0x807f 0..63 0..63 iom-2000 receive transmit 0x6000..0x607f 0x6080..0x80ff 0..127 0..127 pcm receive transmit 0xa000..0xa07f 0xa080..0xa0ff 0..127 0..127
delic peb 20571 mailbox protocol description preliminary data sheet 11-51 2003-08 mailbox register (mgen high) p-write address: 43 h for every entry (four bytes per entry): mailbox register (mdt[x] low) p-write mailbox register (mdt[x] high) p-write bit76543210 (size3) size2 size1 size0 size3..0 amount of following entries within mdt0..7(15) (range: 1..4(8)) bit76543210 id7 id6 id5 id4 id3 id2 id1 id0 id7..0 connection identification bit76543210 dit2 dit1 dit0 sit2 sit1 sit0 sit2..0 source interface type 001 = iom-2 010 = iom-2000 100 = pcm dit2..0 destination interface type 001 = iom-2 010 = iom-2000 100 = pcm
delic peb 20571 mailbox protocol description preliminary data sheet 11-52 2003-08 mailbox register (mdt[x+1] low) p-write mailbox register (mdt[x+1] high) p-write note: values for x are 0, 2, 4, 6, (8, 10, 12, 14) 11.12.1.2 8-bit disconnect command (0x18) this command deactivates a connection between two time slots. parameter: ? amount of following entries for every entry: ? connection identifier mailbox register (mgen high) p-write address: 43 h bit76543210 stsn7 stsn6 stsn5 stsn4 stsn3 stsn2 stsn1 stsn0 stsn7..0 source time slot number bit76543210 dtsn7 dtsn6 dtsn5 dtsn4 dtsn3 dtsn2 dtsn1 dtsn0 dtsn7..0 destination time slot number bit76543210 (size5) size4 size3 size2 size1 size0 size5..0 amount of following bytes within mdt0..7(15) (range: 1..16(32))
delic peb 20571 mailbox protocol description preliminary data sheet 11-53 2003-08 for every entry (one byte per entry): mailbox register (mdt0..7(15)) p-write bit76543210 id7 id6 id5 id4 id3 id2 id1 id0 id7..0 connection identification
delic index preliminary data sheet i-1 2003-08 12 index a applications 1-7 b block diagram 4-2 block diagram of the delic-lc 1-2 boot strap pin setting 4-41 c commands 8-bit connect command 11-50 8-bit disconnect command 11- 52 activation/deactivation com- mand 11-41 finish boot command 11-13 finish initialization command 11-24 ghdlc configuration command 11-22 iom-2000 delay measurement command 11-21 iom-2000 vip channel configu- ration command 11-22 monitor reset command 11-30 read register command 11-17 reset command 11-40, 11-46 search on command 11-29 search reset command 11-30 start boot command 11-13 transmit command 11-30, 11- 41, 11-47 transmit continuous com- mand 11-30, 11-41, 11-48 transmit&receive/receive only command 11-30 write c/i value command 11- 27, 11-38 write data memory command 11-14 write program memory com- mand 11-13 write register command 11-16 d differences delic-lc - delic-pb 4-1 f features delic-lc 1-4 delic-pb 1-4 i indications change detected indication 11- 27, 11-38 error indication 11-15, 11-42, 11-48 fatal error indication 11-48 finish vip channel configuration indication 11-26 firmware version indication 11- 15 iom-2000 delay indication 11- 25 iom-2000 far-end code viola- tion indication 11-24 monitor active indication 11-32 read register indication 11-18 receive continuous indication 11-31, 11-44, 11-49 receive indication 11-31, 11- 44, 11-49 start loading data ram indica- tion 11-15 start loading program ram indi- cation 11-15 transfer ready indication 11- 31 transmit abort indication 11-32 transmit ready indication 11- 43, 11-49 interfaces
delic index preliminary data sheet 12-2 2003-08 p interface 3-24 iom?-2 interface 3-23 iom-2000 3-2 overview 3-1 interrupts 3-26 introduction 1-1 iom-2000 command and status interface 4-7 data interface 4-11 framing bits 4-6 iom-2000 frame structure 3-3 iomu overview of features 4-14 j jtag test interface 3-27 l logic symbol 1-6 p pin definitions 2-3, 2-15 pin diagram 2-1, 2-2 principle block diagram of the delic-pb 1-3 s s/t state machine 3-14 strap pin definitions 2-28 subscriber address 11-4 t transiu initialization 4-3 overview of features 4-3 u upn state machine 3-9 v vip initialization 4-4
delic glossary preliminary data sheet 13-1 2003-08 13 glossary ahv-slic peb 4165 high voltage part of slic cmos complementary metal oxide semiconductor co central office codec coder decoder dc direct current dect digital european cordless telecommunication delic dsp embedded line and port interface controller (peb 20570, peb 20571) dsl digital subscriber line dsp digital signal processor hdlc high-level data link control ieee institute of electrical and electronic engineers info u- and s-interface signal as specified by ansi/etsi i/o input/output iom-2 isdn-oriented modular 2nd generation iom-2000 proprietary isdn inferface for s/t and u p isdn integrated services digital network itu international telecommunications union mubic peb22521 mdsl transceiver mupp peb 31665 16-channel codec digital front end part p micro processor octat-p octal transceiver for u pn -interfaces (peb 2096) lt-s line termination-subscriber lt-t line termination-trunk pll phase-locked loop pbx private branch exchange quad-u peb 2491 4-channel u-transceiver
delic glossary preliminary data sheet 13-2 2003-08 qap peb 3465 equivalent 4-channel analog front end part for mupp quat-s quadrupletransceiver for s/t-interface (peb 2084) slicofi-2 peb 3265 dual channel codec + low voltage part of slic s/t two-wire pair isdn interface tap test access port tbd to be defined

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